Solid state array with supplemental dielectric layer crossover structure

#This invention relates generally to large area solid state imager devices and specifically to address line crossover structures for large area imager devices.

#Solid state imaging devices can be used for detection of incident radiation. Such imager devices typically comprise an array of pixels with an associated matrix of rows and columns of address lines to electrically access each pixel. Each pixel has a photosensor and a switching transistor, such as a thin film transistor (TFT), the gate of which is coupled to a scan line and the source of which (or alternatively, the drain) is coupled to a data line. These address lines are used read the signal from respective pixel photosensors.

#The various components in an imager device are formed in layers on a substrate such that components are sandwiched within the completed structure. For example, scan lines and data lines are disposed in a matrix structure such that data lines overlie scan lines at crossover points in each pixel of the array. Defects in the array, such as short circuits between scan lines and data lines commonly appear in crossover regions. Such defects can seriously degrade imager performance, particularly in high performance imagers such as are used in medical diagnostic imaging.

#The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention itself, however, both as to organization and method of operation, together with further objects and advantages thereof, may best be understood by reference to the following description in conjunction with the accompanying drawings in which like characters represent like parts throughout the drawings, and in which:

#FIG. 1(A) is a plan view of a portion of an array having a crossover region in accordance with the present invention.

#FIG. 1(B) is a cross-sectional view of the crossover region taken along the lines I--I of FIG. 1 (A).

#A solid state array device 100, such as a radiation imager for detecting electromagnetic radiation such as x-rays or the like, or a display device comprising liquid crystal devices, comprises a plurality of pixels 110 (a representative portion of one pixel being illustrated in FIG. 1 (A)) and a plurality of first address lines 140 and a plurality of second address lines 150 that are coupled to respective ones of pixels 110, as illustrated in FIG. 1 (A). By way of example, and not limitation, the invention will be described with respect to a radiation imager using the nomenclature associated with such a device; the invention is similarly applicable to an array structure used in display devices. In a typical imager, each pixel 110 comprises a respective photosensor 120 and a switching transistor 130, such as a thin film transistor (TFT) or the like. In imager 100, first address lines 140 typically are referred to as scan lines and are coupled to a gate 132 of TFT 130; signals on these lines are used to cause the TFT to become conductive or non-conductive. Second address lines 150 are typically referred to as data lines, and are coupled to respective drains 134 of TFTs 130; the source of TFT 130 is coupled to photosensor 120 (as used herein for TFT 130, both the source and drain of the transistor are used for electrical coupling and the specific nomenclature of source and drain is interchangeable). Scan lines 140 and data lines 150 are disposed in the array substantially perpendicular to one another in a matrix arrangement such that data lines 150 overlie scan lines at each pixel in a crossover region 160.

#In accordance with this invention, imager 100 further comprises a crossover region supplemental dielectric layer 170 that is disposed between scan line 140 and data line 150 in crossover region 160. As illustrated in FIG. 1(B), a cross-sectional view of crossover region 160, scan line 140 is disposed on substrate 105 that comprises glass or the like. Scan line 140 typically comprises a conductive material such as aluminum, titanium, molybdenum, or the like, and has a thickness in the range between about 0.1 .mu.m and 1 .mu.m.

#Typically supplemental dielectric layer 170 is disposed directly on scan line 140, with a gate dielectric layer 136 disposed over dielectric layer 170; alternatively, gate dielectric layer 136 is disposed directly on scan line 140 and supplemental dielectric layer 170 is disposed over the gate dielectric layer (dependent on array structure and fabrication techniques, dielectric layer 170 may be disposed directly on scan line 140 or, alternatively, portions of the semiconductor (e.g., silicon) or conductor material (e.g., doped silicon) of the TFT sandwich structure can be disposed between the scan line and dielectric layer 170). Gate dielectric layer 136 extends over crossover region 160 and a channel region 134 of TFT 130 (the channel region includes the area over gate electrode 132), and typically is disposed across the array so as to electrically insulate scan lines 140 from other array components. Gate dielectric layer typically has a thickness in the range between about 0.1 .mu.m and 0.5 .mu.m and comprises an inorganic dielectric material such as silicon oxide, silicon nitride, or silicon oxy-nitride, but may alternatively comprise polyimide or similar polymer. In crossover region 160, data line 150 is disposed over gate dielectric layer 136; in some arrangements, such as illustrated in FIG. 1(A), data line 150 is disposed on a semiconductive layer 138 that is typically formed from the amorphous silicon deposited in the formation of TFT 130. Semiconductive layer 138 typically has a thickness in the range between about 0.05 .mu.m and 0.5 .mu.m. Additional layers (not pertinent to the present invention) of conductive, semiconductive, and dielectric material (e.g., n+ type doped silicon deposited over the silicon) are deposited in the formation of the imager array, but are not shown for ease of illustration.