Method of reducing word line resistance of a semiconductor memory
AssigneeSamsung Electronics Co., Ltd.
InventorsHyeun-Su Kim, Dong-Jae Lee
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Abstract
A semiconductor memory device with a memory array of cells formed as a matrix has bit lines, and word lines driven by word line drivers, where each of the word line drivers simultaneously selects and drives at least two word lines in order to minimize line resistances of the word lines, thereby minimizing a delay time and improving a speed of sensing a cell data. Accordingly a number of the word line drivers is at least one-half a number of the word lines.
Claims13
A process for making a semiconductor memory device having an open bit structure, comprising the steps of:
- forming adjacent pair of word lines each comprised of a plurality of serially coupled layers of polycrystalline silicon forming gate electrodes of a plurality of transistor memory cells;
- forming layers of metal extending substantially parallel to said adjacent pairs of word lines;
- and
- coupling each said adjacent pair of word lines to a different single word line driver.
A process of making a semiconductor memory device having an open bit structure, comprising the steps of:
- forming a plurality of adjacent pairs of word lines with an electrical connection between each said adjacent pair of word lines;
- and
- connecting a different, single word line drivers to each said pair of word lines to enable each said different single word line driver to simultaneously drive corresponding said pair of word lines and to enable each said different single word line driver to drive one of the word lines of each said pair of adjacent word lines in response to corresponding selected word line signals, said one of said plurality of word lines exhibiting a reduced resistance.
A process of forming a semiconductor memory device, comprising the steps of:
- forming a matrix of memory cells with a plurality of word lines, each one of said plurality of word lines capable of accessing a different plurality of said memory cells;
- and
- connecting a different, single word line driver to at least two adjacent word lines from said plurality of word lines for enabling said single word line driver to select and drive said two adjacent word lines connected in parallel.
The process of making a semiconductor memory device having an open bit line structure, comprising the steps:
- forming a memory array of memory cells;
- forming a first word line comprising a plurality of first, serially coupled word line resistances to access a first plurality of memory cells in said memory array;
- forming a second word line comprising a plurality of second, serially coupled word line resistances to access a second plurality of memory cells in said memory array different from said first plurality of memory cells;
- and
- connecting a single word line driver to one end of said first word line and said second word line, for enabling said single word line driver to drive one of said first word line and said second word line in response to a word line selection signal and a driver selection signal.
A process of making a memory device, comprising the steps:
- forming a memory array of memory cells;
- forming successive pairs of first and second word lines each pair comprised of a plurality of first layers of a first material forming gate electrodes of the memory cells in said memory array and a second layer of a second material extending substantially parallel to, and being connected to each pair of said first and second word lines;
- and
- connecting a single word line driver to said second layer of said second material for communication with each pair of said first and second word lines, for enabling said single word line driver to drive one of said first word line and said second word line during operation of said memory device.
Dependencies are inferred from the claim text.