Method for forming a stable semiconductor device having an arsenic doped ROM portion

A process for forming an arsenic doped semiconductor integrated circuit device comprising the steps of:

• forming an oxide layer on an upper surface of a substrate, the substrate comprising a semiconductor material of a first conductivity type and having a first doped region of the first conductivity type extending from the upper surface and a second doped region of a second conductivity type extending from the upper surface;
• forming a polysilicon layer on the oxide layer;
• patterning the polysilicon layer in a dry etch system;
• annealing the substrate after the patterning step;
• doping the substrate with arsenic after annealing the substrate;
• and
• forming a MOSFET device in one of the first doped region and the second doped region.

A method for forming semiconductor device comprising the steps of:

• providing a substrate of a first conductivity type, the substrate having a first well region of the first conductivity type extending from an upper surface of the substrate and a second well region of a second conductivity type extending from the upper surface;
• forming a tunnel oxide layer on the upper surface;
• forming a floating gate layer on the tunnel oxide layer;
• patterning the floating gate layer to form a floating gate region over a portion of the first well region, wherein the patterning includes dry etching the floating gate layer;
• annealing the substrate after the patterning step in a non-oxidizing environment;
• introducing arsenic into selected areas of the first well region to form a ROM portion of the semiconductor device after the step of annealing the substrate;
• and
• forming a first MOSFET device in the first well region and a second MOSFET device in the second well region.