Process for manufacturing integrated circuit with power field effect transistors

A manufacturing process for insulated gate field effect transistors with vertical current flow, comprising the steps of:

• epitaxial growth on a monocrystalline silicon substrate of a layer of silicon having a first type of conductivity;
• oxidation of said epitaxial layer to produce a field oxide layer;
• patterning said field oxide layer to form a mask for implantation of second-conductivity-type dopants, to produce a deep-body region;
• exposing said epitaxial layer in active area locations;
• definition and implantation of body and source regions;
• wherein said source region is implanted through an oxidation resistant masking layer, which is also used to mask an oxidation process which forms a thickened oxide over substantially all of said source regions;
• and
• growth of a gate oxide layer, and deposition, doping, and definition of a polycrystalline silicon layer thereover, to form a patterned insulated gate layer;
• wherein said step of definition and implantation of the body region and source regions is performed before said steps of growth of a gate oxide layer and deposit of the gate polycrystalline silicon layer;
• whereby the possibility of occurrence of short circuits between the gate and source regions is reduced and the parasitic capacitance between the gate and source regions is also reduced.