US 5,630,165 AGranted

Servo system controlled by master and second processors through memory being accessed for read and write by processors in separate portions respectively

AssigneeAdvanced Micro Devices, Inc.

InventorsSaf Asghar, Brett Stewart

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Abstract

A servo loop control apparatus having a master microprocessor and at least one autonomous streamlined signal processor is disclosed. The architecture provides a general purpose controller for use in systems where intensive servo signal processing is required and is well suited to applications where multiple servo control loops operate simultaneously. The operation of the streamlined signal processors is autonomous from the master processor so that critical functions can be dedicated to the streamlined signal processors. This eliminates complex interrupt management and tedious real time scheduling constraints, simplifies system design and improves system performance. The architecture provides an integrated mechanism for implementing multiple, concurrent, complex signal processing and embedded control functions, such as complete servo-mechanism management for high performance disk storage systems.

Claims22

Dependent claims

A servo loop control apparatus comprising:

input circuitry arranged to receive signals from a servo loop to be controlled;
output circuitry arranged to provide signals to a servo loop to be controlled;
a master processor to control said apparatus, said master processor being connected via a bus to a memory and having write access at any time to any location in a first portion of said memory and read access at any time to any location in said first portion and a second portion of said memory;
a second processor, said second processor communicatively coupled to at least one of said input and said output circuitry and programmed to operate autonomously of said master processor, said second processor being dedicated to specific, pre-programmed servo loop control tasks and being connected to said memory with write access at any time to any location in said second portion of said memory and read access to any location in said first and second portions of said memory, said second processor comprises means for executing repetitive preprogrammed servo loop processing instructions without interruption, thereby maintaining operation of a servo loop independent of said master processor;
and
a plurality of vector registers, said vector registers forming a means for interrupting said servo loop processing in said second processor under a limited set of predefined conditions;
wherein said at least one of said input circuitry and said output circuitry are controlled by said master processor and said second processor through said memory.

4 more elements

A method of servo loop control, the method comprising the steps of:

receiving into input circuits signals from a servo loop to be controlled;
through output circuitry providing signals to a servo loop to be controlled;
executing overall control of said servo loop with a master processor via a bus to a memory;
operating a second processor, connected to said bus and communicatively coupled to at least one of said input circuits and said output circuitry, autonomously of said master processor and dedicating said second processor to specific, pre-programmed servo loop control tasks;
executing in said second processor repetitive preprogrammed servo loop processing instructions without interruption, thereby maintaining operation of a servo loop independent of said master processor;
interrupting said servo loop processing in said second processor under a limited set of predefined conditions through a plurality of servo registers;
and
controlling said input circuitry and said output circuitry by said master processor and said second processor through a memory having a first portion and a second portion, said master processor at any time having access to write data to said first portion of said memory and to read data from said first portion and said second portion of said memory, said second processor at any time having access to write data to said second portion of said memory and to read data from both said first and said second portions of said memory.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/673,317Filed 28 Jun 1996 · continuation
Priority: 3 Dec 1992
Granted: 13 May 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification22 codes

G11B 7/126
Optical beam sources therefor, e.g. laser control circuitry specially adapted for optical storage devices; Modulators, e.g. means for…
G05B 19/4148
Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller:…
G11B 19/00
Driving, starting, stopping record carriers not specifically of filamentary or web form
G11B 21/083
Access to indexed tracks or parts of continuous track: on discs