Computer having a single bus supporting multiple bus architectures operating with different bus parameters

A data processing system comprising,

• a plurality of external bus devices connected to a processor for communicating with the processor at different times, said bus devices operating with different timing parameters that include different information transfer rates associated with different bus bandwidths, and
• a plurality of components for integration on a common semiconductor chip, including
• the processor,
• a plurality of special-purpose buses each connected to the processor and to one of the external devices and each operating at a different bus bandwidth corresponding to the bus bandwidth associated with the bus device to which it is connected,
• a single common bus connecting the plurality of external bus devices to the plurality of special-purpose buses, and
• bus processing means for controlling the bus bandwidth of the common bus, to correspond to the bus bandwidth associated with the external bus device that is communicating with the processor at any one of said different times.

A data processing system for communicating with a plurality of external devices, said devices operating with different timing parameters that include different information transfer rates associated with different bus bandwidths, the data processing system comprising

• a processor;
• a plurality of special-purpose buses each connected to the processor and to one of the external devices and each operating at a different bus bandwidth corresponding to the bus bandwidth associated with the bus device to which it is connected,
• a single common bus connecting the plurality of external bus devices to the plurality of special-purpose buses, and
• bus processing means for controlling the bus bandwidth of the common bus, to correspond to the bus bandwidth associated with the external bus device that is communicating with the processor at any one of said different times.