Array processor dotted communication network based on H-DOTs

A parallel SIMD or MIMD array processor communication network, comprising:

• a plurality of processing elements interconnected in an array topology configuration, each of the processing elements having at least two ports for communication with other processing elements;
• a physical link providing an interconnection among four processing elements of said plurality of processing elements, said physical link having four ports respectively coupled to one of the ports for each of the four processing elements, and having a common low impedance connection among the four ports of the physical link such that any said one of the ports for each of the four processing elements is coupled by a low impedance path through said physical link to another one of the ports of the four processing elements over the physical link;
• and
• a communications control mechanism in each of the four processing elements operative in transferring a message of the synchronous type or of the routed type from one of the four processing elements to another one of the four processing elements over the physical link;
• wherein said communications control mechanism includes a routing algorithm executed by the processing elements for transferring messages of the routed type, wherein said routing algorithm comprises an ACCEPT routine, and a KEEP routine, wherein the routing ACCEPT routine of a processing element determines when the processing element should access a message on either of two ports of the processing element;
• and
• wherein one of said processing elements having a first address has ports to a multidimensional quadrant, and the routing ACCEPT routine accepts a message having a given address if the given address is either the first address of the processing element, or else an address of any processing element located in the multidimensional quadrant.