US 5,630,160 AGranted

Floating point exponent compare using repeated two bit compare cell

AssigneeTexas Instruments Incorporated

InventorsRichard Simpson, Erick Oakland

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Abstract

A magnitude comparator employs plural layers of repeated circuits which are scalable to any size. The magnitude comparator indicates whether two multibit inputs are equal, and if not equal indicates if a first multibit input is greater than a second multibit input. A single bit comparator circuit receives a corresponding bit of the two multibit inputs. Each single bit comparator generates an A=B output equal to the exclusive NOR of the two inputs and an A>B output equal to the first input. The magnitude comparator includes at least one two bit comparator circuit disposed in at least one layer. Each two bit comparator circuit includes an A[0]=B[0] input, an A[0]>B[0] input, an A[1]=B[1] input and an A[1]>B[1] input. Each two bit comparator circuit generates an A=B output of an AND of signals received at the A[0]=B[0] and A[1]=B[1] inputs. Each two bit comparator circuit generates an A>B output equal to the A[1]>B[1] input if the A[0]=B[0] input is "1" and equal to the A[0]>B[0] input if the A[0]=B[0] input is "0".

Claims8

Dependent claims

A magnitude comparator for first and second N bit data words comprising:

a set of N single bit comparators, each single bit comparator having an A input receiving one bit of the first N bit data word, a B input receiving a corresponding bit of the second N bit data word, each single bit comparator forming a signal on an A=B output having a first digital state if a signal received on said A input equals a signal received on said B input and supplying said signal received on said A input to an A>B output;
a set of N-1 two bit comparators disposed in at least one layer, each two bit comparator having an A[0]=B[0] input, an A[0]>B[0] input, an A[1]=B[1] input and an A[1]>B[1] input, each two bit comparator generating at an A=B output an AND of signals received at said A[0]=B[0] input and said A[1]=B[1] input and generating at an A>B output a signal equal to said signal received on said A[1]>B[1] input if said signal received at said A[0]=B[0] input has a first digital state and generating at said A>B output a signal equal to said signal received on said A[0]>B[0] input if said signal received at said A[0]=B[0] input has a second digital state opposite to said first digital state;
a first layer of said two bit comparators each having said A[0]=B[0] input connected to said A=B output of a first one of said single bit comparators, said A[0]>B[0] input connected to said A>B output of said first single bit comparator, said A[1]=B[1] input connected to said A=B output of a second single bit comparator corresponding to a next most significant bit than said first single bit comparator, said A[1]>B[1] input connected to said A>B output of said second single bit comparator;
subsequent layers of said two bit comparators each having said A[0]=B[0] input connected to said A=B output of a first two bit comparator of a prior layer, said A[0]>B[0] input connected to said A>B output of said first two bit comparator, said A[1]=B[1] input connected to said A=B output of a second comparator of a prior layer corresponding to a next most significant bit than said first two bit comparator, said A[1]>B[1] input connected to said A>B output of said second comparator;
a last layer of two bit comparators consisting of a single two bit comparator, said A=B output of said single two bit comparator of said last layer indicating whether said first N bit data word equals said second N bit data word and said A>B output of said single two bit comparator of said last layer indicating whether said first N bit data word is greater than said second N bit data word if said A=B output indicates inequality.

2 more elements

A method of comparing for first and second N bit data words comprising the steps of:

generating a first determination for each N bits of said first and second N bit data words by
forming an A=B output indicating whether corresponding bits of said first and second N bit data words are equal, and
forming an A>B output equal to said corresponding bit of said first N bit data input;
generating a second determination for each pair of bits of said first determination by
forming an A=B output indicating whether said A=B outputs of two prior determinations are equal,
forming an A>B output equal to a prior most significant A>B output if a prior most significant A=B output has a first digital state, and
forming an A>B output equal to a prior least significant A>B output if said prior most significant A=B output has a second digital state opposite to said first digital state;
generating subsequent determinations for each pair of bits of prior determinations by
forming an A=B output indicating whether said A=B outputs of two prior determinations are equal,
forming an A>B output equal to a prior most significant A>B output if a prior most significant A=B output has a first digital state, and
forming an A>B output equal to a prior least significant A>B output if said prior most significant A=B output has a second digital state opposite to said first digital state;
a last of said subsequent determinations
forming an A=B output indicating whether said first N bit data word equals said second N bit data word, and
forming an A>B output indicating whether said first N bit data word is greater than said second N bit data word if said A=B output indicates inequality.

11 more elements

Dependencies are inferred from the claim text.