Central processing unit including inhibited branch area

Abstract

A central processing unit includes an instruction register storing instruction codes, a timing control unit controlling timings of steps of execution of an instruction, an execution unit executing an operation on data and temporarily storing data, the execution unit having a program counter and a data bus, a decoder decoding instruction codes read from the instruction register and controlling the instruction register, the timing control unit and the execution unit, and a next enable unit receiving an indication signal indicating proceeding to a next instruction should be performed and controlling outputting of the indication signal to the instruction register and the timing control unit based on first and second signals. The first signal is supplied from the decoder and instructing data on the data bus to be input to the program counter. The second signal is supplied from the execution unit and indicating whether a counter value of the program counter is an odd number or an even number.

Dependencies are inferred from the claim text.