Computer organization for multiple and out-of-order execution of condition code testing and setting instructions

A computer system unit, comprising:

• bus means for providing a stream of instructions including condition code setting and condition code testing instructions;
• a buffer to store instructions until they are issued;
• scheduling and issuing unit means for scheduling and issuing multiple concurrent instructions, including condition code setting instructions and condition code testing instructions, which are out-of-order with respect to instruction stream order within a sufficiently short time so that the cycle time of said computer system unit is not limited by the operation time of the scheduling and issuing unit means;
• said scheduling and issuinq unit means including means for binding a condition code testing instruction to an immediately precedinq condition code setting instruction and preventing issue of a condition testing instruction until completion of the condition code setting instruction with which it is bound;
• multiple condition code registers;
• means to attach a tag (CC.sub.-- tag) to a condition code setting instruction;
• and
• means for using such condition code setting instruction to address a specific condition code register when the condition code setting instruction executes.

A computer system unit, comprising:

• bus means for providing a stream of instructions including condition code setting and condition code testing instructions;
• a buffer to store instructions until they are issued;
• scheduling and issuing unit means for scheduling and issuing multiple concurrent instructions, including condition code setting instructions and condition code testing instructions, which are out-of-order with respect to instruction stream order within a sufficiently short time so that the cycle time of said computer system unit is not limited by the operation time of the scheduling and issuing unit means;
• said scheduling and issuing unit means including means for binding a condition code testing instruction to an immediately preceding condition code setting instruction and preventing issue of a condition testing instruction until completion of the condition code setting instruction with which it is bound;
• multiple condition code registers;
• means for preventing issuing of a condition code setting instruction or condition code testing instruction if an uncompleted preceding instruction in the scheduling and issuing unit has a tag which matches a tag of said condition code setting instruction or condition code testing instruction.