Programmable systolic array system arranged in a found arrangement for passing data through programmable number of cells in a time interleaved manner

An adaptive beamforming system, comprising:

• a sensor array for providing sample vectors of sensor sample signals from sensor devices comprising said array;
• a source of one or more steering vectors each defining a steering direction;
• an initialization device for providing a set of initialization data parameters;
• a processor array responsive to said sample vectors, said one or more steering vectors and said set of parameters, said processor array for computing adaptive weights to be applied to said sample vectors for each said steering vector;
• means for providing delayed replicas of said sample vectors;
• and
• beamforming means for applying said adaptive weights to said delayed replicas of said sample vectors to result in nominally formed beams;
• said processor array comprising a linear systolic array of computation cells, each cell comprising a plurality of vector rotation stages, each said computation cell includes a programmable microcode sequencer for controlling arithmetic operation of said cell, and wherein each said cell further includes a multi-function random access memory storage function for providing temporary storage of data under control of said sequencer, said microcode sequencer comprising programmable means responsive to said set of initialization data parameters to configure respective cells according to said set of data parameters so as to control data flow into and out of each said cell, the arithmetic operation of each said cell and the internal storage of data in said random access memory storage function.

A programmable processor system for performing extremely high throughput matrix arithmetic operations on linear systems of equations in real time, said processor system comprising:

• a linear systolic array of computation cells, each cell comprising a plurality of vector rotation stages;
• and
• programmable means responsive to configuration data to configure respective cells according to said configuration data, said data determining which cells are operational during said arithmetic operations, wherein said linear array is programmable in operational cell length, and wherein during array operation, all information passed between said computation cells is in the form of packets;
• said computation cells comprising means for recognizing and responding to a plurality of different types of packets, said packet types including a constraint vector packet type including constraint vector data used by said array in performance of said matrix arithmetic operations, and a backsolve packet type indicating all sample data and constraint vector data has been entered into said array, said cells comprising means responsive to said backsolve packet to commence operations to solve said linear systems of equations for an output data vector.

An adaptive beamforming system, comprising:

• a sensor array for providing sample vectors of sensor sample signals from sensor devices comprising said array;
• a source of one or more steering vectors each defining a steering direction;
• an initialization device for providing a set of initialization data parameters;
• a processor array responsive to said sample vectors, said one or more steering vectors and said set of parameters, said processor array for computing adaptive weights to be applied to said sample vectors for each said steering vector;
• means for providing delayed replicas of said sample vectors;
• and
• beamforming means for applying said adaptive weights to said delayed replicas of said sample vectors to result in nominally formed beams;
• said processor array comprising a linear systolic array of computation cells, each cell comprising a plurality of vector rotation stages, and programmable means responsive to said set of initialization data parameters to configure respective cells according to said set of data parameters, said set determining which cells are operational during said arithmetic operations, wherein said linear array is programmable in length, said computation cells programmably arranged in a folded arrangement wherein data is passed successively through a programmable number of said cells according to said set of data parameters in a first direction and back through said cells in a second direction in a time interleaved manner, and wherein said cells further include programmable latency delay means for delaying transfer of data between cells in order to achieve proper interleaving of said data, said configuration data further includes latency programming data, said programmable latency delay means responsive to said latency programming data to set said delay means in accordance with said latency programming data.