Communication protocol between master and slave device with register information sharing

In a selective call receiver, a method for full duplex data transference between a microprocessor and a slave device included within the selective call receiver and coupled by a serial peripheral interface (SPI), the method comprising the steps of:

• the slave device monitoring sources of events in the selective call receiver;
• the slave device updating status information contained in a status register in response to at least one of the events occurring within the selective call receiver;
• the slave device providing an interrupt signal to the microprocessor over the SPI in response to updating the status information;
• the microprocessor, in response to the interrupt signal, providing a communication initiation signal to the slave device over the SPI, wherein the communication initiation signal addresses no registers of the slave device;
• and
• the slave device, in response to the communication initiation signal and during the first clock cycle following transmission of the communication initiation signal, automatically providing a portion of the status information contained in the status register to the microprocessor over the SPI without first receiving an address of the status register from the microprocessor.

An electronic device having full duplex data transference between semiconductor devices, comprising:

• a master device for providing to a slave device a communication initiation signal that addresses no registers included in the slave device;
• a serial peripheral interface (SPI) for coupling the master device to the slave device to provide the communication initiation signal thereover;
• and
• the slave device, comprising:
• means for receiving information signals from sources;
• a status register for storing information;
• means for updating the information stored in the status register in response to the information signals;
• and
• means for automatically providing the updated information to the master device over the SPI in response to the communication initiation signal without first receiving an address of the status register from the master device, wherein the updated information is provided by the slave device during the first clock cycle following the communication initiation signal.

A selective call receiver having full duplex data communication between semiconductor devices, comprising:

• a microprocessor for providing a communication initiation signal that addresses no registers included in any other device of the selective call receiver;
• a support chip coupled to the microprocessor for receiving the communication initiation signal, for receiving interrupt signals from interrupt sources, for storing interrupt information corresponding to the interrupt signals in a register, and for automatically providing, in response to the communication initiation signal, portion of the interrupt information included in the register to the microprocessor without first receiving an address of the register from the microprocessor;
• and
• a serial peripheral interface (SPI) coupled between the microprocessor and the support chip for providing the communication initiation signal from the microprocessor to the support chip, for transferring the interrupt information from the support chip to the microprocessor, and for providing to the support chip, as a function of full duplex data transference between the support chip and the microprocessor, meaningless information to which the support chip does not respond, wherein the meaningless information does not address the register, and wherein the transference of both the meaningless information and the interrupt information occurs during the first clock cycle following the communication initiation signal .