Pipelined processor with register renaming hardware to accommodate multiple size registers

A microprocessor including register renaming apparatus, the microprocessor having at least one instruction pipeline with a plurality of stages for processing a stream of instructions, and having a plurality of logical registers, the stream of instructions including write instructions that when processed addressably write to a logical register having multiple addressable portions, comprising:

• a plurality of physical registers exceeding in number the plurality of logical registers, and
• register translation circuitry coupled to said at least one instruction pipeline and to said physical registers, said register translation circuitry being operable to allocate, for each of at least some of said write instructions processed, a physical register to said logical register based at least in part on which of said addressable portions of said logical register is addressed by said write instruction;
• wherein, for a current write instruction that is processed when a write is pending to said logical register in response to a previous write instruction, said register translation circuitry selectively allocates a new physical register to said logical register based on which of said addressable portions of said logical register are addressed by said previous and current instructions.