Method and apparatus for invalidating a cache while in a low power state

A processor having a core for use in a computer system having a bus and an external clock generator for providing a frequency input clock signal, said processor comprising:

• a phase locked loop (PLL) circuit that generates at least one core clock signal for clocking the core in response to said frequency input clock signal;
• a central processing unit (CPU) that processes data synchronous with said at least one clock signal;
• a cache memory having a plurality of lines, said cache memory coupled to said CPU to store information for use by said CPU;
• a first logic circuit that places said processor in a reduced power consumption state, wherein said first logic circuit includes a control logic that disables said at least one core clock signal to the remainder of the processor when placing said processor in the reduced power consumption state, wherein the PLL continuously runs during the reduced power consumption state;
• a second logic circuit that powers up the processor out of said reduced power consumption state to run an invalidation cycle in said cache memory to invalidate information in the cache memory, wherein said second logic circuit places the processor back into the reduced power consumption state after performing the invalidation cycle.

A computer system comprising:

• a bus that communicates data in the computer system;
• a phase locked loop (PLL) circuit that generates at least one bus clock signal for clocking bus operations and at least one core clock signal;
• a processor coupled to said bus that processes information synchronous to said at least one core clock signal and transfers data externally according to said at least one bus clock signal, wherein said processor includes a cache memory that stores information, and further wherein the processor is capable of being in a reduced power consumption state;
• a memory coupled to said bus that stores information;
• a peripheral coupled to said bus to perform a designated function, wherein said peripheral accesses said memory, such that data is written into said memory;
• a circuit logic coupled to said bus and the PLL circuit that monitors when said peripheral accesses said main memory and generates a signal indicating that the peripheral has accessed the main memory;
• wherein said processor powers up from the reduced power consumption state in response to the signal being asserted, wherein an invalidation cycle occurs on said cache memory to invalidate data in the cache memory, and wherein the processor re-enters the reduced power consumption state after the invalidation cycle.

In a processor clocked by a frequency input clock signal, a circuit for allowing a core of said processor to invalidate data in an internal cache memory, said circuit comprising:

• a phase detector that receives said frequency input clock signal and a feedback signal and for generating a first signal in response thereto that is a measure of the phase difference between said frequency input clock signal and said feedback signal;
• a voltage generator that generates a voltage control signal in accordance with said first signal;
• a voltage-controlled oscillator that generates at least one core clock signal in response to said voltage control signal, the frequency of said at least one core clock signal varying in accordance with the level of said feedback voltage;
• a first logic circuit that generates a masking signal in response to said at least one core clock signal, said masking signal being a first state or a second state;
• and
• a second logic that generates at least one bus clock signal in response to said at least one core clock signal and said masking signal, such that said second logic generates said at least one bus clock signal when said masking signal is in said first state and masks said at least one bus clock signal when said masking signal is in said second state, such that said at least one bus control signal has a frequency which is a multiple of said at least one core clock signal, one of said at least one bus clock signal being said feedback signal, such that said at least one core clock signal is a predetermined multiple of the frequency of said frequency input clock signal,
• a circuit that enables and disables said at least one core clock signal, wherein said circuit disables said at least one core clock signal when placing said processor in the reduced power consumption state, such that the PLL and said at least one bus clock signal are continuously running during the reduced power consumption state, and wherein said circuit enables said at least one core clock signal to power up said processor out of said reduced power consumption state to perform an invalidation cycle on said cache memory to invalidate information in the cache memory,
• wherein said circuit disables said at least one core clock signal to place the processor back into the reduced power consumption state after performing the invalidation cycle.

An integrated circuit comprising:

• a cache memory that stores information duplicated in a main memory;
• a first logic circuit that places said integrated circuit in a reduced power consumption state;
• and
• a second logic circuit temporarily powering up said integrated circuit out of said reduced power consumption state to run an invalidation cycle in said cache memory to invalidate information therein to maintain cache coherence with the main memory, the second logic circuit restoring the integrated circuit to the reduced power consumption state after running the invalidation cycle.