Method and apparatus for reducing power consumption according to bus activity as determined by bus access times

A computer arrangement, comprising:

• a plurality of Peripheral Component Interconnect (PCI) buses,
• a plurality of bus controllers for controlling the PCI buses, each bus controller including a signal generator for generating an asynchronous signal,
• a plurality of peripheral devices connected to the PCI buses, each peripheral device including a signal generator for generating an asynchronous signal,
• a power management unit (PMU) controller connected to a first of the PCI buses, the PMU controller including a signal detector for detecting an asynchronous signal generated by any one of the bus controllers or peripheral devices, the PMU controller stopping the sending of a clock signal to the bus controllers and the peripheral devices when all of the plurality of PCI buses are idle and restarting the clock signal when an asynchronous signal is detected by the PMU controller, and
• a memory device provided by the PMU controller for storing a head configuration and a first time constant corresponding to a specific one of the peripheral devices and a second time constant corresponding to the length of time needed for the PMU controller to read the head configuration from the specific peripheral device, the specific peripheral device being one of the peripheral devices which is connected to the PCI bus which has the most intervening buses between itself and the first PCI bus, wherein if the second time constant is smaller than the first time constant plus a predetermined time constant greater than or equal to zero, the PMU controller stops the sending of the clock signal to the bus controllers and the peripheral devices.

A computer arrangement, comprising:

• a plurality of Peripheral Component Interconnect (PCI) buses,
• a plurality of bus controllers for controlling the PCI buses, each bus controller including a signal generator for generating an asynchronous signal,
• a plurality of peripheral devices connected to the PCI buses, each peripheral device including a signal generator for generating an asynchronous signal,
• a power management unit (PMU) controller connected to a first of the PCI buses, the PMU controller including a signal detector for detecting an asynchronous signal generated by any one of the bus controllers or peripheral devices, the PMU controller stopping the sending of a clock signal to the bus controllers and the peripheral devices when all of the plurality of first PCI buses are idle and restarting the clock signal when an asynchronous signal is detected by the PMU controller, and
• a memory device provided by the PMU controller for storing a head configuration and a first time constant corresponding to a specific one of the peripheral devices and a second time constant corresponding to the length of time needed for the PMU controller to read the head configuration from the specific peripheral device, the first time constant determined by the time needed for the PMU controller to read the head configuration when all the peripheral devices other than the specific peripheral device are disabled, wherein if the second time constant is smaller than the first time constant plus a predetermined time constant greater that or equal to zero, the PMU controller stops the sending of the clock signal to the bus controllers and the peripheral devices.