US 5,630,108 A · Frequency independent PCMCIA control signal timing

Abstract

A bus interface timing unit responsive to a system clock signal having a frequency that is selectable among a plurality of frequencies. The bus interface timing unit provides timing signals to a bus interface unit that performs functions involving control signals having predetermined timing requirements, such timing requirements being substantially independent of the frequency of the system clock signal. The bus interface timing unit includes a signal generator (20) which is responsive to the system clock signal, and which generates the control signals. These control signals include at least one event signal controlling a time duration in which a predetermined event occurs. Also included is a control unit (10), responsive to a signal representative of the selected frequency of the system clock signal, that controls the signal generator such that the event signal timing is generated in accordance with the predetermined requirements the selected frequencies.

Claims10

Dependent claims

In a data processing system having a system clock that clocks data processing events at a system clock frequency, a bus interface timing unit, responsive to a system dock value signal representing the frequency of said system dock that is selectable among a plurality of frequencies, for providing control signals to a bus interface unit that controls the transfer of signals across said interface, under control of at least one of said control signals having predetermined timing requirements, wherein said timing requirements are substantially independent of the frequency of said system clock signal and depend upon an operation to be performed in said data processing system, comprising:

signal generation means, responsive to said system clock signal, for generating said at least one control signal;
and
means responsive to a signal representative of the selected frequency of said system clock signal and for controlling said signal generation means such that said control signal is generated in accordance with said predetermined timing requirements for said selected frequencies, regardless of the frequency of said system clock.

A bus interface timing unit for a data processing system having a system clock that clocks data processing events at a system clock frequency, responsive to a system clock value signal representing the frequency of said system dock that is selectable among a plurality of frequencies, for providing control signals to a bus interface unit that controls the transfer of signals across said interface under control of at least one of said control signals, said transfer having predetermined timing requirements, wherein said timing requirements are substantially independent of the frequency of said system clock signal and depend upon an operation to be performed in said data processing system, comprising:

a timing decoder, responsive to said system clock value signal and responsive to an instruction for an operation to be performed in said data processing system, and providing timing control signals representing said predetermined timing requirements;
and
a timing generator, responsive to said timing control signals and generating transfer timing signals for controlling the timing of the transfer of signals across said interface in conformance with said predetermined timing requirements.

Dependencies are inferred from the claim text.

Frequency independent PCMCIA control signal timing

Life of this patent

Frequency independent PCMCIA control signal timing

Life of this patent

Abstract

Claims10