System for loading PLL from bus fraction register when bus fraction register is in either first or second state and bus unit not busy

In a micro processor including a bus fraction register having an encoded value stored therein, said encoded value placing a contents of said bus fraction register in either an initial state, a first state or a second state, said initial state indicating a default bus clock speed, said first state indicating a first bus clock speed and said second state indicating a second bus clock speed, data processing logic that includes a number of units arranged as an instruction pipeline, said units being clocked by an internal clock running at a first frequency and operating with an input/output (I/0) bus clocked by an I/O clock running at a second frequency, said second frequency being a fraction of said first frequency, one of said units being a bus unit which controls bus cycles in said pipeline and generates a bus unit busy (BBSY) signal upon a condition that said bus unit is busy with bus cycles, a method comprising the steps of:

• A. generating a stop clock signal upon a condition that said contents of said bus fraction register is in said first state or said second state;
• B. polling said bus unit busy (BBSY) signal line to determine if said BBSY signal line is asserted or not asserted, said polling being initiated in response to said stop clock signal;
• C. asserting a stop mode signal upon a condition that said contents of said bus fraction register is in said second state and upon a condition that said BBSY signal line is not asserted;
• D. signaling said internal clock and said I/O clock to stop in response to a no operation (NOP) micro instruction placed in said pipe line, to indicate that said pipeline is clear of pending instructions;
• and,
• E. executing a number of NOP micro instructions, the number being determined by the amount of time required by said I/O clock to stop.

A clock apparatus comprising:

• a bus fraction register logic which stores an encoded value which indicates either an initial state indicating a default bus clock speed, a first state indicating a first bus clock speed or a second state indicating a second bus clock speed;
• said bus fraction register logic including a decoder for decoding said encoded value and for asserting a stop mode line upon a condition that said first state or said second state is decoded;
• an internal clock that runs at a first frequency;
• an internal bus clocked by said internal clock;
• an input/output clock that runs at a second frequency, said second frequency being a fraction of said first frequency;
• an input/output bus clocked by said input/output clock;
• a data processing logic connected to said internal bus, said data processing logic including a number of units arranged as an instruction pipeline, said units being connected to said internal bus;
• an external clock;
• a phase-locked loop clock connected to and driven by said external clock;
• said phase-locked loop clock having a wakeup input for starting operation of said phase-locked loop clock;
• said phase-locked loop clock storing a bus fraction value that sets the operating frequency of said phase-locked loop clock;
• an external interrupt signal line;
• wakeup logic connected to said external interrupt signal line, to said stop mode line and to said external clock, said wakeup logic having a wakeup output that is asserted upon a condition that said external interrupt signal line is asserted and said stop mode line is asserted;
• and
• said wakeup output being connected to said wakeup input of said phase-locked loop clock.

A clock apparatus comprising:

• a bus fraction register logic means which stores an encoded value which indicates either an initial state indicating a default bus clock speed, a first state indicating a first bus clock speed or a second state indicating a second bus clock speed;
• said bus fraction register logic means including a decoder for decoding said encoded value and for asserting a stop mode line upon a condition that said first state or said second state is decoded;
• an internal clock means for providing at a first frequency;
• an internal bus clocked by said internal clock;
• an input/output clock means for providing a second frequency, said second frequency being a fraction of said first frequency;
• an input/output bus clocked by said input/output clock;
• a data processing logic means connected to said internal bus, said data processing logic including a number of units arranged as an instruction pipeline, said units being connected to said internal bus;
• an external clock;
• a phase-locked loop clock means connected to and driven by said external clock;
• said phase-locked loop clock means having a wakeup input for starting operation of said phase-locked loop clock;
• said phase-locked loop clock including means for storing a bus fraction value for setting the operating frequency of said phase-locked loop clock;
• an external interrupt signal line;
• wakeup logic means connected to said external interrupt signal line, to said stop mode line and to said external clock, said wakeup logic having a wakeup means for asserting a wakeup output upon a condition that said external interrupt signal line is asserted and said stop mode line is asserted;
• and
• said wakeup output being connected to said wakeup input of sake phase-locked loop clock means.

In a processor including a bus fraction register having a first state or a second state, said first state indicating a first bus clock speed and said second state indicating a second bus clock speed, a bus unit which controls bus cycles for said processor and generates a bus unit busy signal upon a condition that said bus unit is busy with bus cycles, a method comprising the steps of:

• A. generating a stop clock signal;
• B. polling said bus unit busy signal to determine if said bus unit busy signal is asserted or not asserted, said polling being initiated in response to said stop clock signal;
• C. asserting a stop mode signal upon a condition that said contents of said bus fraction register is in said second state and upon a condition that said bus unit busy signal is not asserted;
• and
• D. signaling an internal clock and an input/output (I/O) clock to stop in response to a no operation (NOP) micro instruction placed in a pipeline of the processor, to indicate that said pipeline is clear of pending instructions, wherein said internal clock is running at a first frequency and said I/O clock is running at a second frequency, said second frequency being a fraction of said first frequency.

An apparatus comprising:

• a bus fraction register which stores an encoded value indicating a first state or a second state, the first state indicating a first bus clock speed and the second state indicating a second bus clock speed;
• a data processing logic coupled to an internal bus, said data processing logic including a number of units arranged as an instruction pipeline, said units being coupled to said internal bus;
• an external clock;
• a phase-locked loop clock coupled to and driven by said external clock;
• said phase-locked loop clock having a wakeup input for starting operation of said phase-locked loop clock;
• said phase-locked loop clock storing a bus fraction value that sets the operating frequency of said phase-locked loop clock;
• an external interrupt signal line;
• wakeup logic coupled to said external interrupt signal line, to said stop mode line and to said external clock, said wakeup logic having a wakeup output that is asserted upon a condition that said external interrupt signal line is asserted and said stop mode line is asserted;
• said wakeup output being coupled to said wakeup input of said phase-locked loop clock;
• an internal clock that runs at a first frequency;
• said internal bus being clocked by said internal clock;
• An input/output clock that runs at a second frequency, said second frequency being a fraction of said first frequency;
• and
• said input/output bus being locked by said input/out clock.