Simulating multi-phase clock designs using a single clock edge based system

A sequential logic circuit comprising:

• a data node;
• a system clock node;
• a phase generator having an input terminal coupled to the system clock node and an output terminal;
• a first multiple-phase latch mapping circuit having a data input terminal coupled to the data node, an enable terminal coupled to the output terminal of the phase generator and an output terminal;
• a combinational logic block having an input terminal coupled to the output terminal of the first multiple-phase latch mapping circuit and having an output terminal;
• and
• a second multiple-phase latch mapping circuit having a data input terminal coupled to the output terminal of the combinational logic block, an enable terminal coupled to the output terminal of the phase generator and an output terminal.

An apparatus for converting a multiple-phase circuit to a single-clock-edge circuit comprising:

• a first control switch having a first input terminal coupled to a data node, a second input terminal, a control terminal coupled to receive a phase clock signal having a phase clock frequency and an output terminal;
• a latch having an input terminal coupled to the first control switch output terminal, an output terminal coupled to the first input terminal of the first control switch and a clock terminal coupled to receive a system clock signal having a system clock frequency which is a multiple of the phase clock frequency;
• and
• a second control switch having a first input terminal coupled to the data node, a second input terminal coupled to the output terminal of the latch, a control terminal coupled to receive the phase clock signal and an output terminal.

An apparatus for converting a multiple-phase circuit to a single-clock-edge circuit comprising:

• an input multiplexer controlled by a phase clock signal having a phase clock frequency for selecting an input signal between a data signal and a feedback signal;
• a flip-flop coupled to the input multiplexer to receive the input signal and controlled by a system clock signal having a system clock frequency which is a multiple of the phase clock frequency for latching the input signal on a clock edge of the system clock signal;
• and
• an output multiplexer controlled by the phase clock signal for selecting an output signal between the data signal and the latched signal, the latched signal being fed back to the input multiplexer as the feedback signal.

A system for converting the operation of a multiple-phase, level-sensitive transparent device to an edge-sensitive operation comprising:

• an input switch having a first input terminal coupled to the multiple-phase, level-sensitive transparent device for receiving an operating signal, having a second input terminal for receiving a feedback signal, having a control terminal for receiving a phase signal of a multiple-phase timing signal, and having an output terminal;
• an edge-sensitive trigger device having an input terminal coupled to the output terminal of the input switch, having a control terminal coupled to receive a system clock signal, and having an output terminal coupled to the second input terminal of the input switch for supplying a feedback signal;
• and
• an output switch having a first input terminal coupled to the multiple-phase, level-sensitive transparent device for receiving an operating signal, having a second input terminal coupled to the output terminal of the edge-sensitive trigger device, having a control terminal for receiving the phase signal of the multiple-phase timing signal, and having an output terminal for generating an edge-sensitive output signal synchronous with the system clock signal.