Non-volatile memory array controller capable of controlling memory banks having variable bit widths

A memory controller comprising:

• a first output buffer configured to drive data from a first bank of non-volatile memory on a first byte lane of a local bus;
• a second output buffer configured to drive data from said first bank of non-volatile memory on a second byte lane of said local bus;
• a data routing unit configured to selectively route data from a first byte lane of a memory data bus to either said first output buffer or to said second output buffer;
• and
• an interface control unit configured to receive a local bus read signal and a local bus address signal, wherein said interface control unit is configured to generate a memory read signal and a memory address signal in response to said local bus read signal and said local bus address signal such that data is provided from said first bank of non-volatile memory simultaneously to said first byte lane and to a second byte lane of said memory data bus if a memory size input signal indicates that said first bank of non-volatile memory has a first predetermined bit width, and wherein said interface control unit is configured to generate a first and a second memory read signal in response to said local bus read signal such that data is sequentially provided from said first bank of non-volatile memory through said first byte lane of said memory data bus to said data routing unit if said memory size input signal indicates that said first bank of non-volatile memory has a second predetermined bit width.

A method for operating a memory controller, wherein said memory controller is connected to a first memory bank, to a second memory bank, to a first byte lane of a local bus, and to a second byte lane of said local bus, said method comprising the steps of:

• providing a control signal to said memory controller indicative of the bit width of said second memory bank;
• executing a memory read cycle on said local bus;
• determining whether said memory read cycle corresponds to a memory location contained by said first memory bank or by said second memory bank;
• reading a first byte and a second byte of data from said first memory bank simultaneously and providing said first and second bytes of data to said first and second byte lanes of said local bus if said memory read cycle corresponds to a location within said first memory bank;
• and
• if said memory read cycle corresponds to a memory location contained by said second memory bank:
• reading a first and a second byte of data from said second memory bank simultaneously and providing said first and second bytes of data to said first and second byte lanes of said local bus if said control signal indicates that said second memory bank has a first predetermined bit width;
• or
• reading a first byte of data from said second memory bank;
• providing said first byte of data to a data routing unit;
• selectively routing said first byte of data from said data routing unit to a first buffer;
• reading a second byte of data from said second memory bank subsequent to the reading of said first byte of data;
• providing said second byte of data to said data routing unit;
• selectively routing said second byte of data from said data routing unit to a second buffer;
• and
• providing said first and second bytes of data from said first buffer and second buffer to said local bus simultaneously.