Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order

A controller for a synchronous DRAM comprising:

• a sorting unit for receiving memory requests and sorting said memory requests based on their address;
• a throughput maximizing unit for processing said memory requests to the synchronous DRAM in response to scheduling which maximizes the use of data slots by the synchronous DRAM;
• and
• a control block for receiving a controller clock signal and developing an SDRAM clock signal by dividing said controller clock signal with a programmable divisor value.

A system for interfacing a processing device with a synchronous DRAM comprising:

• means for developing memory requests from the processing device;
• means for tagging said memory requests to indicate the order in which they are provided by the processing device;
• and
• a controller for maximizing throughput of said memory requests from the processing device to the synchronous DRAM based on scheduling constraints of the synchronous DRAM and arbitrating between conflicting memory requests so that data slots used by the synchronous DRAM are maximized.

A method for controlling a synchronous DRAM comprising the steps of:

• (a) receiving memory requests and sorting said memory requests based on their addresses;
• (b) tagging said memory requests to indicate a sending order thereof before said memory requests are received at said step (a);
• and
• (c) maximizing throughput of said memory requests to the synchronous DRAM so that use of data slots by the synchronous DRAM is maximized.

A method for controlling a synchronous DRAM comprising the steps of:

• (a) receiving memory requests and sorting said memory requests based on their addresses;
• (b) maximizing throughput of said memory requests to the synchronous DRAM so that use of data slots by the synchronous DRAM is maximized;
• and
• (c) receiving a controller clock signal and developing an SDRAM clock signal by dividing said controller clock signal with a programmable divisor value.

A method for interfacing a processing device with a synchronous DRAM, comprising the steps of:

• (a) developing memory requests from the processing device;
• (b) tagging said memory requests to indicate the order in which they are provided by the processing device;
• and
• (c) maximizing throughput of said memory requests from the processing device to the synchronous DRAM based on scheduling constraints of the synchronous DRAM and arbitrating between conflicting memory requests so that the data slots used by the synchronous DRAM are maximized.