Method for use with a data coherency protocol allowing multiple snoop queries to a single snoop transaction and system therefor

A system for use with a data coherency protocol comprising:

• decode circuitry receiving a single bus transaction from a bus and a memory response signal from a memory subsystem, the decode circuitry generating a snoop response responsive to the single bus transaction, to the memory response signal and to a coherency protocol, the decode circuitry operating at a first clock frequency, the bus operating at a second clock frequency, the ratio of the first clock frequency to the second clock frequency greater than or equal to two, the decode circuitry generating the snoop response each cycle of the first clock cycle occurring during a predetermined cycle of the second clock signal for the single bus transaction, the single bus transaction comprising a memory address and an operation to be performed upon a data block indexed by the memory address, the memory response representative in a first logic state of an inability to determine a presence or an absence of a data word associated with the memory location in the memory subsystem;
• select circuitry receiving the snoop response generated by the decode circuitry, the select circuitry initially generating a control signal corresponding to a first logic state, the select circuitry generating a control signal corresponding to a first logic state at the beginning of the predetermined cycle of the second clock signal, the select circuitry generating the control signal corresponding to a second logic state responsive to a first occurrence of a first predetermined snoop response;
• and
• latching circuitry receiving the snoop response generated by the decode circuitry and receiving the control signal generated by the select circuitry, the latching circuitry selectively storing the snoop response or a previously stored snoop response, the latching circuitry storing the snoop response responsive to the first logic state of the control signal, the latching circuitry storing the previously stored snoop response responsive to the second logic state of the control signal, the latching circuitry outputting the latched snoop response at a predetermined time to the bus.