US 5,630,094 A · Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions

Abstract

A computer system having an integrated bus bridge and memory controller circuit and method for enabling access to a shared memory with high bandwidth data streaming are disclosed. The integrated bus bridge and memory controller circuit performs a series of snoop ahead transactions over a first bus during access transactions to the shared memory that originate over a second bus and thereby enables high bandwidth data streaming on the second bus. The integrated bus bridge and memory controller circuit includes a peripheral write buffer that buffers write data received over the second bus and that stores a snoop done flag for the write data that indicates whether a corresponding snoop ahead transaction for the write data is complete. The integrated bus bridge and memory controller circuit further includes a peripheral read prefetch buffer that prefetches read data during read transactions over the second bus only after a corresponding snoop ahead transaction for the read data is complete.

Claims8

Dependent claims

A computer system, comprising:

a processor and a cache memory each coupled to a first bus;
a main memory;
a bus agent coupled to a second bus;
and
a bus bridge and memory controller circuit coupled to the first bus and the second bus, the bus bridge and memory controller circuit enabling read and write access to the main memory from the first bus and the second bus and also including buffer circuitry for buffering write data, received over the second bus and targeted for the main memory, the bus bridge and memory controller circuit initiating and performing a plurality of snoop ahead transactions to the cache memory over the first bus during memory access transactions originated on the second bus and targeted for the main memory, the bus bridge and memory controller circuit including circuitry for storing, for each of the plurality of snoop ahead transactions, a snoop status indication for indicating if a respective one of the plurality of snoop ahead transactions corresponding to a respective one of the memory access transitions has completed.

2 more elements

A bus bridge and memory controller circuit for use in a computer system having a processor and cache memory, each coupled to a first bus, and a bus agent coupled to a second bus, the bus bridge and memory controller circuit coupled to the first bus and the second bus, the computer system further including a main memory coupled to the bus bridge and memory controller circuit, the bus bridge and memory controller circuit comprising:

state machine circuitry for enabling read and write access to the main memory from the first bus and the second bus and for initiating and performing a plurality of snoop ahead transactions to the cache memory over the first bus during memory access transactions originated over the second bus and targeted for the main memory;
buffer circuitry for buffering write data received over the second bus and targeted for the main memory;
and
circuitry for storing, for each of the plurality of snoop ahead transactions, a snoop status indication for indicating if a respective one of the plurality of snoop ahead transactions corresponding to a respective one of the memory access transactions has completed.

1 more element

Dependencies are inferred from the claim text.

Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions

Life of this patent

Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions

Life of this patent

Abstract

Claims8