High density buffer architecture and method
AssigneeSeiko Epson Corporation
InventorsChong M. Lin, Raymond J. Werner
Life of this patent
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AssigneeSeiko Epson Corporation
InventorsChong M. Lin, Raymond J. Werner
Estimating the term…
A buffer memory architecture, method, and chip floor plan allows for significant reduction in the physical area required for a buffer memory of any given size in a microelectronic device. Buffer applications wherein random access to the buffered data is not required use a CMOS dynamic serial memory with p-channel devices supplied with a voltage less positive than the voltage supplied to their respective n-wells. In a particular embodiment, three memory stages are used in a cascaded fashion. The first and third memory stages store data on a parallel basis, while the second memory stage stores data on a serial basis. The second memory stage can be fabricated using much less chip area per bit than the first and third memory stages. Significant area reduction is achieved because the second memory stage eliminates addressing overhead associated with conventional high-density memory schemes, and low voltage power supplies permit relaxation of latch-up prevention layout rules.
A memory system, adapted for implementation in a microelectronic device, said memory system comprising:
A buffer memory layout floor plan comprising:
A method for storing data in a disk drive, comprising the steps of:
A memory buffer for use with a computer storage device, said memory buffer comprising:
A method for storing data in a computer storage device, said method comprising the steps of:
A method for retrieving data from a computer storage device, said method comprising the steps of:
Dependencies are inferred from the claim text.