Apparatus for and methods of providing a safe-stop mode for a microprocessor operating in a PSRAM-memory environment

Apparatus for controlling access to pseudo-static memory within which pseudo-static memory data may be stored and from which such stored data may be retrieved during active periods of the pseudo-static memory, the pseudo-static memory remaining addressable and active during periods of externally applied refresh pulses and becoming self-refreshing and non-responsive during periods without externally applied refresh pulses, the apparatus comprising:

• refresh means for applying refresh pulses to the pseudo-static memory to maintain the pseudo-static memory in an active and addressable state;
• access means for accessing the pseudo-static memory in response to receipt of a non-maskable interrupt signal from one of a plurality of NMI sources, said access means coupled to said refresh means to operatively inhibit application of refresh pulses to the pseudo-static memory during an address-inactive state of the pseudo-static memory;
• and
• switching means for intercepting a non-maskable interrupt signal from one of the plurality of NMI sources to said access means wherein said switching means is operative, when the pseudo-static memory is in an address-inactive state, to intercept an initial non-maskable interrupt signal occurring at the conclusion of an address-inactive state of the pseudo-static memory, to convert the intercepted non-maskable interrupt signal to a reset pulse, to re-route the reset pulse to the access means, and to continue inhibiting said access means from accessing the pseudo-static memory until the pseudo-static memory is reset to the active and addressable state.

A method for controlling access to pseudo-static memory within which pseudo-static memory data may be stored and from which such stored data may be retrieved during active periods of the pseudo-static memory, the pseudo-static memory remaining addressable and active during periods of externally applied refresh pulses, and becoming self-refreshing and non-responsive during periods without externally applied refresh pulses during address-inactive periods of the pseudo-static memory, the method comprising the steps of:

• using an access means to access the pseudo-static memory in response to receipt of a non-maskable interrupt signal from one of a plurality of NMI sources when the pseudo-static memory is addressable and active;
• inhibiting the access means from accessing the pseudo-static memory during the address-inactive periods;
• intercepting a non-maskable interrupt signal from one of the plurality of NMI sources to the access means occurring at the conclusion of an address-inactive period;
• converting the intercepted non-maskable interrupt signal to a reset signal;
• and
• re-routing the reset signal to the access means.

An apparatus having an active configuration and an inactive configuration, from either of which said apparatus is capable of responding to a nonmaskable interrupt ("NMI") signal from a plurality of NMI sources, said apparatus comprising:

• (a) first memory means, having pseudo-static memory, for retaining first information for use by said apparatus after said apparatus assumes said active configuration;
• said first memory means having first refresh means for refreshing said pseudo-static memory when said apparatus is in said inactive configuration;
• (b) second memory means, having "permanent" memory, for retaining second information configured to operatively activate said apparatus from said inactive configuration to said active configuration;
• (c) second refresh means for refreshing said pseudo-static memory when said apparatus is in said active configuration;
• and
• (d) switching means for:
• (1) intercepting an NMI signal from one of the plurality of NMI sources when said apparatus is in said inactive configuration and converting said intercepted NMI signal to a reset pulse,
• (2) re-routing said reset pulse, and
• (3) delaying accessing of said first memory means in response to said re-routed reset pulse until said apparatus has been activated to said active configuration from said inactive configuration.

A method for activating an apparatus from an inactive configuration, including a safe stop mode resulting from either a total shut-down mode or a temporary power interruption mode, to an active configuration, wherein said apparatus has a "permanent" memory having start-up instructions, a pseudo-static memory that is internally refreshed as said apparatus assumes said inactive configuration and is externally refreshed when said apparatus is in said active configuration, and a microprocessor capable of accessing the "permanent" memory and the pseudo-static memory, and wherein said apparatus is capable of responding to a non-maskable interrupt ("NMI") signal from a plurality of NMI sources, said method comprising the steps of:

• (a) intercepting an NMI signal from one of the plurality of NMI sources and converting the intercepted NMI signal to a reset pulse;
• (b) re-routing said reset pulse such that the microprocessor accesses the start-up instructions in response thereto such that the apparatus in activated from the inactive configuration to the active configuration;
• and
• (c) delaying accessing of the pseudo-static memory until the apparatus has been activated to the active configuration from the inactive configuration.