Virtual to physical address translation
AssigneeHewlett-Packard Company
InventorsRajiv Gupta, Richard J. Carter
Life of this patent
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AssigneeHewlett-Packard Company
InventorsRajiv Gupta, Richard J. Carter
Estimating the term…
A high-speed address translation look-aside buffer (TLB) for translating an explicit address, comprised of an index, a TLB index, and an offset, into a physical address. The TLB cooperates with a space register file having a plurality of space registers, each space register having an indirect address for a corresponding index value. The TLB includes a memory organized as N TLB entries, each entry having an entry space tag, a virtual tag, a valid bit, and a physical page number. A comparator is coupled to each entry which compares only the TLB index to the virtual tag. Each TLB entry further includes a matching bit memory for pre-storing the results of comparing the contents of the entry space tag with the contents (indirect address) of the space registers. The contents of the matching bit memories are then selected during the memory translation process to indicate the result of the prior comparison. The matching bit memories thus eliminate the need to access the space registers during the address translation process thereby substantially reducing the virtual-to-physical address translation time.
A method of translating an virtual address comprised of an indirect address and an explicit address into a physical address comprising:
An address translation apparatus for translating an explicit address within an address space into a physical address, the explicit address comprised of an index, a TLB index, and an offset, the translation apparatus comprising:
In a virtual memory system having a space register file for storing indirect addresses, a method of speeding TLB translation of an explicit address having base bits and index bits into a physical address, the method comprising:
An address translation apparatus for translating a virtual address into a physical address, the virtual address including an indirect address and an explicit address, the explicit address comprised of a first index and a second index, said apparatus comprising a memory having N entries, each entry having an entry space tag, a virtual tag, and a physical page number, each of said entries including at least
Dependencies are inferred from the claim text.