Apparatus systems and methods for controlling electronic memories
AssigneeHewlett-Packard Company
InventorsBryan D. Marietta, Douglas A. Oppedahl
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Abstract
Memory control circuitry is provided which includes circuitry for generating a sequence of gray code values. Counter circuitry is coupled to the gray code circuitry and controls the duration of assertion of each of the generated gray code values. Bus circuitry is also coupled to the gray code circuitry for transmitting the gray code values generated by circuitry. Programmable logic array circuitry is also coupled to the bus circuitry for transmitting, receiving and decoding each of the gray code values and providing at least one memory control signal in response.
Claims17
Memory control circuitry comprising:
- gray code circuitry for generating a sequence of gray code values;
- operation type circuitry for generating an operation type signal;
- duration control circuitry coupled to said gray code circuitry for controlling the duration of assertion of each of said gray code values;
- transmitting circuitry coupled to said gray code circuitry and said operation type circuitry for transmitting said gray code values and said operation type signal;
- gate array circuitry for receiving said sequence of gray codes and said operation type signal and generating in response a first selected one of a timed sequence of operation type signals;
- and
- programmable array logic for receiving said sequence of gray codes and said operation type signal and generating in response a second selected one of said timed sequence of operation type signals.
A memory system comprising:
- control circuitry comprising:
- circuitry operable to generate a clocked sequence of gray code values;
- circuitry operable to control the duration of the assertion of each of said gray code values;
- and
- circuitry operable to generate a memory operation type control signal;
- and
- memory circuitry coupled to said control circuitry comprising:
- gate array circuitry operable to receive said sequence of gray codes and said memory operation type control signal and generate in response a first selected one of a timed sequence of memory operation type control signals;
- and
- programmable array of logic circuitry operable to receive said sequence of gray codes and said memory operation type control signal and generate in response a second selected one of said memory operation type control signals.
Circuitry for reducing the number of signals being passed through a connector coupling first and second circuits comprising:
- gray code generation circuitry forming a portion of said first circuit and operable to generate a timed sequence of gray code states;
- memory control generation circuitry forming a portion of said first circuit and operable to generate a memory control signal;
- and
- decoder circuitry forming a portion of said second circuit and comprising:
- gate array circuitry operable to receive said sequence of gray codes and said memory control signal and generate in response a first selected one of a timed sequence of memory control signals;
- and
- programmable array logic operable to receive said sequence of gray codes and said memory control signal and generate in response a second selected one of said memory control signals.
Dependencies are inferred from the claim text.