Microprocessor with improved instruction cycle using time-compressed fetching
AssigneeSony Corporation
InventorNobuhisa Watanabe
Life of this patent
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Abstract
A microcomputer includes an instruction decoder and a program counter. The instruction decoder decodes fetched instructions and outputs a control signal ordering execution of the fetched instruction. The control signal from the instruction decoder includes a component controlling fetch cycles which triggers a fetch cycle at the beginning of each instruction cycle to fetch the operand for the instruction currently being executed and midway through each instruction cycle to fetch the OP code for the next instruction. The program counter is responsive to the triggering of each fetch cycle to increment its counter value so as to keep the counter value consistent with the address being accessed in each fetch cycle.
Claims8
A method of operating a microprocessor, said processor having a pipe-line architecture for allowing a first byte of data defining a first selected instruction that is to be executed during at least one respective machine cycle to be fetched from a memory during an earlier machine cycle for completion of execution of a second selected instruction previously fetched from said memory, said first and second selected intructions being herein referred to as the current and preceding instructions, respectively, and being selected from a plurality of instructions, respective ones of said plurality of instructions being plural-byte instructions as a result of including at least a second byte of operand data, wherein all of said bytes of each said plural-operand instruction to be executed are sequentially fetched, each said byte of each said instruction being stored at and fetched from a respective sequential address in said memory, each said address of a byte to be fetched being indicated by a counter, said method comprising the steps of:
- providing each said instruction to include an operation code in its first byte, wherein said operation code for each said plural-byte instruction includes information indicating that a time-compressed fetching of each said second byte and of any such third byte of the same instruction is to be sequentially performed when that instruction is said current instruction;
- fetching said first byte of the current instruction from said memory at the end of said machine cycle for said completion of said preceding instruction, and simultaneously incrementing said counter to indicate the next byte stored therein;
- and
- when said operation code of said current instruction indicates that it is one of said plural-byte instructions, subsequently fetching said second byte of said current instruction from said memory at the end of the first half of the first said at least one machine cycles for said current instruction, and simultaneously incrementing said counter for indicating the next byte to be fetched at the end of the second half of said first machine cycle of said current instruction, as a result of said information in said operation code of said current instruction;
- wherein if said operation code in said first byte of said current instruction does not indicate that said time-compressed fetching is to occur, namely that the current instruction does not have such a second and third byte, said counter is incremented simultaneously with said fetching of said operation code thereof at said end of said machine cycle for completing said previous instruction, without any further incrementing of said counter at the end of the first half of said first machine cycle for said current instruction;
- and
- wherein when said current instruction is a 2-byte instruction the execution of which requires said operand of said second byte thereof only during said second half of said first machine cycle of said current instruction, execution of said current instruction is completed in said second half of said first machine cycle.
A method of operating a microprocessor, said processor having a pipe-line architecture for allowing a first byte of data defining a first selected instruction that is to be executed during at least one respective machine cycle to be fetched from a memory during an earlier machine cycle for completion of execution of a second selected instruction previously fetched from said memory, said first and second selected instructions being herein referred to as the current and preceding instructions, respectively, and being selected from a plurality of instructions, respective ones of said plurality of instructions being plural-byte instructions as a result of including at least a second byte of operand data, wherein all of said bytes of each said plural-operand instruction to be executed are sequentially fetched, each said byte of each said instruction being stored at and fetched from a respective sequential address in said memory, each said address of a byte to be fetched being indicated by a counter, said method comprising the steps of:
- providing each said instruction to include an operation code in its first byte, wherein said operation code for each said plural-byte instruction includes information indicating that a time-compressed fetching of each said second byte and of any such third byte of the same instruction is to be sequentially performed when that instruction is said current instruction;
- fetching said first byte of the current instruction from said memory at the end of said machine cycle for said completion of said preceding instruction, and simultaneously incrementing said counter to indicate the next byte stored therein;
- and
- wherein when said operation code of said current instruction indicates that it is one of said plural-byte instructions, said second byte of said current instruction is subsequently fetched from said memory at the end of the first half of the first of said at least one machine cycle for said execution of said current instruction, and said counter is simultaneously incremented for indicating the next byte to be fetched at the end of the second half of said first machine cycle of said current instruction, as a result of said information in said operation code of said current instruction;
- wherein if said operation code in said first byte of said current instruction does not indicate that said time-compressed fetching is to occur, namely that the current instruction does not have such a second and third byte, said counter is incremented simultaneously with said fetching of said operation code thereof at said end of said machine cycle for completing said previous instruction, without any further incrementing of said counter at the end of the first half of said first machine cycle for said current instruction;
- and
- wherein said current instruction is one said plural-byte instructions, specifically a 3-bite instruction, said third byte is fetched at the end of said second half of said first machine cycle of said current instruction, and the execution of said current instruction is completed in a second machine cycle immediately following said first machine cycle.
Dependencies are inferred from the claim text.