System for converting data in little endian to big endian and vice versa by reversing two bits of address referencing one word of four words
AssigneeKabushiki Kaisha Toshiba
InventorNobuyuki Ikumi
Life of this patent
Estimating the term…
Loading patent…
AssigneeKabushiki Kaisha Toshiba
InventorNobuyuki Ikumi
Estimating the term…
A data processing device including: data processor handling at one time a plurality of data such as instructions each consisting of one word; a plurality of input ports for inputting a plurality of data; a memory for storing temporarily the data inputted through the input pins, each of whose elements consisting of one byte; and exclusive OR gates for designating each of the elements of the memory. Each portion of a memory element is referenced by a byte address each consisting two bits wherein when the information device can handle data formed in a Little-endian-type, in which the address are increased in sequence from the byte on the Least significant Bit (LSB), and the data is formed in a big-endian-type, in which the byte address are increased in sequence from the byte on the Most Significant Bit (MSB), the exclusive OR gates reverse some of the bits of each byte address.
A data arranging device for arranging plural n-byte data words while transferring the plural n-byte data words from an external memory means to a data processing means, comprising:
A data processing device connected to a memory for receiving four words of data in parallel from said memory in a format for either a little-endian system or a big-endian system, one word of data being composed of four bytes of data, said data processing device converting four bytes of data in little-endian format to four bytes of data in big-endian format or vice versa when said data processing device generates data in big-endian format while data received from said memory is in little-endian format or vice versa, said data processing device comprising:
Dependencies are inferred from the claim text.