Decoder for decoding multiple instructions in parallel

A multiple instruction decoder for simultaneously decoding multiple macroinstructions, said multiple instruction decoder coupled to receive a plurality of macroinstructions having a format defined by a predetermined instruction set in a predefined sequence, said multiple instruction decoder comprising:

• (a) a first decoder capable of decoding all of said plurality of macroinstructions of said instruction set, including
• circuitry to decode a macroinstruction within said predetermined instruction set into a plurality of micro-operations and to output at least two of said plurality of micro-operations in parallel, and
• a first input coupled to receive a first macroinstruction;
• (b) a second decoder including
• circuitry to decode a macroinstruction within a first subset of frequently used macroinstructions of said predetermined instruction set into one or more microoperations, and
• a second input coupled to receive a second macroinstruction;
• and
• (c) a third decoder including
• circuitry to decode a macroinstruction within a second subset of frequently used macroinstructions of said predetermined instruction set into one or more microoperations, and
• a third input coupled to receive a third macroinstruction.

A multiple instruction decoding method for decoding a plurality of macroinstructions in parallel and responsive thereto for outputting a plurality of micro-operations, said macroinstructions having a format defined by a predetermined instruction set, said multiple instruction decoding method comprising the steps of:

• a) supplying a first macroinstruction to a full decoder capable of decoding all of said plurality of macroinstructions of said instruction set and decoding said first macroinstruction therein into a plurality of micro-operations, wherein the step of supplying a first macroinstruction comprises the steps of applying said first macroinstruction to a plurality of XLAT PLAs and decoding said first macroinstruction therein to supply a plurality of first Cuops in response thereto;
• and
• b) in parallel with the step a, supplying a second macroinstruction to a partial decoder capable of decoding a first subset of frequently used macroinstructions of said instruction set, and decoding said second macroinstruction therein into a micro-operation, wherein the step of supplying the second macroinstruction comprises the steps of applying said second macroinstruction to an XLAT PLA and decoding said second macroinstruction therein to supply a second Cuop in response thereto;
• c) applying said first macroinstruction to a field extractor which, responsive thereto supplies first macro-alias data to a macro-alias register, said field extractor also supplying to said macro-alias register having a plurality of first alias bits corresponding thereto responsive to whether the corresponding macro-alias data is aliased to other macro-alias data;
• d) applying said first Cuop and said first macro-alias data and said first alias bit to a first alias multiplexer that, responsive thereto outputs one or more first Auops;
• (e) applying said second macroinstruction to a field extractor which, responsive thereto supplies second macro-alias data to a second macro-alias register having a plurality of second alias bits corresponding thereto responsive to whether the corresponding macro-alias data is aliased to other macro-alias data;
• and
• (f) applying said second Cuop, said second alias bits, and said second macro-alias data to a second alias multiplexer which, responsive thereto, outputs a second Auop.

A multiple instruction decoder for decoding a plurality of macroinstructions in parallel and responsive thereto for outputting a plurality of micro-operations, said macroinstructions having a format defined by a predetermined instruction set, said multiple instruction decoder comprising:

• a) steering means for supplying a first macroinstruction and a second macroinstruction;
• b) full decoding means coupled to said steering means to receive said first macroinstruction, decode it therein into a plurality of micro-operations, and to output at least two of said plurality of micro-operations in parallel, wherein said full decoding means includes
• a plurality of XLAT PLA means for decoding said first macroinstruction to supply a plurality of first Cuops in response thereto,
• a first field extractor means, responsive to said first macroinstruction, for supplying first macro-alias data and a plurality of first alias bits corresponding thereto, said first alias bits responsive to whether the corresponding macro-alias data is aliased to other macro-alias data, and
• a first alias multiplexer means coupled to receive said Cuop, said first alias bits and said first macro-alias data, and responsive thereto, to output one or more first Auops;
• and
• c) a partial decoding means for decoding a subset of frequently used macroinstructions within said instruction set, said partial decoding means being coupled to said steering means to receive said second macroinstruction and decode it therein into a micro-operation, wherein said first partial decoding means includes
• XLAT PLA means for decoding said second instruction therein to supply a Cuop in response thereto,
• a field extractor means, responsive to said second macroinstruction, for supplying second macro-alias data and a plurality of second alias bits corresponding thereto, said alias bits responsive to whether the corresponding macro-alias data is aliased to other macro-alias data, and
• a second alias multiplexer means coupled to said second Cuop, said second alias bits, and said second macro-alias register, and responsive thereto, to output a second Auop.