Personal computer with processor reset control

A personal computer system comprising:

• a high speed data bus;
• an input/output data bus;
• a resettable microprocessor coupled to said high speed data bus;
• volatile memory coupled to said high speed data bus for volatile storage of data;
• storage memory devices;
• a storage controller coupled to said high speed data bus and to said storage memory devices for regulating communications with said storage memory devices;
• and
• a bus interface controller coupled to said high speed data bus and to said input/output data bus for providing communications between said high speed data bus and said input/output data bus,
• said bus interface controller providing for arbitration between said resettable microprocessor and said storage controller for access to said high speed data bus, and providing for arbitration among said high speed data bus and any devices coupled directly to said input/output data bus for access to said input/output data bus,
• said bus interface controller further recognizing receipt at said bus interface controller of a reset signal (HOTRESET) intended to initiate a reset of said microprocessor and delaying generation of a reset signal (CPU.sub.-- RESET) to said microprocessor until after said bus interface controller has gained control of said high speed data bus and said input/output bus from all of the devices and said microprocessor and said storage controller by the exchange of hold and hold acknowledge signals (CPU.sub.-- HOLD and CPU.sub.-- HLDA).

A personal computer system comprising:

• a high speed data bus;
• a microprocessor coupled directly to said high speed data bus;
• a numeric co-processor coupled directly to said high speed data bus;
• volatile memory coupled directly to said high speed data bus for volatile storage of data;
• storage memory devices for nonvolatile storage of data;
• a storage controller coupled directly to said high speed data bus and to said storage memory devices for regulating communications with said storage memory devices;
• an input/output data bus;
• an input/output controller coupled directly to said input/output data bus;
• a digital signal processor coupled directly to said input/output data bus;
• a video signal processor coupled directly to said input/output data bus;
• and
• a bus interface controller coupled to said high speed data bus and to said input/output data bus for providing communications between said high speed data bus and said input/output data bus,
• said bus interface controller providing for arbitration among said microprocessor and said storage controller coupled directly to said high speed data bus for access to said high speed data bus, and providing for arbitration among said input/output controller and said digital signal processor and said video signal processor coupled directly to said input/output data bus and said high speed data bus for access to said input/output data bus,
• said bus interface controller further recognizing receipt at said bus interface controller of a reset signal (HOTRESET) intended to initiate a reset of said microprocessor and delaying generation of a reset signal (CPU.sub.-- RESET) to said microprocessor until after said bus interface controller has gained control of said high speed data bus and said input/output bus from all of said microprocessor and said storage controller and said input/output controller and said digital signal processor and said video signal processor by the exchange of hold and hold acknowledge signals (CPU.sub.-- HOLD and CPU.sub.-- HLDA).