Write combining buffer for sequentially addressed partial line operations originating from a single instruction

A microprocessor comprising:

• a bus;
• a memory coupled to said bus for storing data and instructions;
• a fetch and issue unit coupled to said bus for fetching data and instructions from said memory, decoding said instruction to determine if said instruction operates on an block of data strings, each of said data strings being smaller than a line of data, and issuing a write-combining micro-instruction if said decoding indicates that said instruction operates on such an block of data strings, said line of data comprising a unit of data most efficiently transferred by the bus;
• an execution unit coupled to said bus and said fetch and issue unit for executing said instructions to process said data, said execution unit generating write operations corresponding to one of said write-combining micro-instructions;
• a bus unit comprising a buffer which comprises a line of data coupled to said bus and said execution unit for combining data from at least one write combining operation with data from at least one said write combining operation corresponding to said write-combining micro-instruction into a data set when said buffer contains data from at least one previous write combining operation and writing data from write combining operation corresponding to said write-combining micro-instruction into said buffer when said buffer does not contain any data, said write combining operations comprising write combining operations corresponding to one of said write-combining micro-instructions, such that data is combined for select write-combining micro-instructions that comprise a plurality of write operations and said data set is transmitted over said bus in one write operation.

In a computer system having a memory means for storing data and instructions, a processing means for processing said data and said instructions, and a communication means for transmitting said data and said instructions between said processing means and said memory means, a write combining means for combining write data comprising:

• an operation determination means for decoding an instruction to determine whether said instruction operates on a block of data strings, each of said data strings being smaller than a line of data, said line of data comprising a unit of data most efficiently transferred by the bus;
• an address determination means for determining whether an address of a write operation matches a tag entry of said write combining means;
• a write means coupled to said operation determination means and said address determination means for writing data corresponding to said write operation to said write combining means if said write operation operates on a block of data strings and if said address matches said tag entry;
• a combining means coupled to said write means for combining a plurality of said data of said write operations to generate a combined set of data such that data is combined for select instructions that comprise a plurality of write operations;
• a storage means coupled to said combining means for storing said combined set of data to said memory in a single write operation.

A computer system comprising:

• a bus;
• a memory coupled to said bus for storing data and instructions;
• a microprocessor coupled to said bus for processing said data and instructions, said microprocessor comprising:
• a fetch and issue unit coupled to said bus for fetching data and instructions from said memory, decoding said instruction to determine if said instruction operates on a block of data strings, each of said data strings being smaller than a line of data, and issuing a write-combining micro-instruction if said decoding indicates that said instruction operates on a block of said data strings, said line of data comprising a unit of data most efficiently transferred by the bus;
• an execution unit coupled to said bus and said fetch and issue unit for executing said instructions to process said data, said execution unit generating write operations corresponding to one of said write-combining micro-instructions;
• a bus unit comprising a buffer which comprises a line of data coupled to said bus and said execution unit for combining data from at least one write combining operation with data from at least one said write combining operation corresponding to said write-combining micro-instruction into a data set when said buffer contains data from at least one previous write combining operation and writing data from write combining operation corresponding to said write-combining micro-instruction into said buffer when said buffer does not contain any data, said write combining operations comprising write combining operations corresponding to one of said write-combining micro-instructions, such that data is combined for select instructions that comprise a plurality of write operations and said data set is transmitted over said bus in one write operation.