US 5,630,054 A · Method and apparatus for storing and retrieving error check information

Abstract

A method and apparatus by which the partial error check value for all preceding data in a sector is updated each time a new data item is written into a data buffer during a transfer from a host computer to a system storage device. The partial check value is written into the buffer location following the location containing the most recently buffered data item from the associated sector. Thus, after the entire sector has been transferred into the buffer, the final check value for that sector will be available in the buffer location following the location containing the last written data from the associated sector. Upon readback of a sector from the storage device, the sector size is longer by one data item since the appended check value is treated as the last data item of the sector. When the sector is read back from the storage device, the check value is again updated with the entry of each data item. When the access is complete, the stored check value is compared with the newly-calculated value to determine whether an error has occurred. The present invention offers improved performance by eliminating some hardware and software elements needed to calculate and store the check value for a sector.

Claims28

Dependent claims

In a computer system having a host computer, a storage subsystem and a plurality of storage devices, wherein the storage subsystem includes a control logic, a data buffer and a plurality of bus controllers, a method for calculating and storing a check value associated with a transfer of a block of data from the host computer to the data buffer, the method comprising the steps of:

a) providing a first memory device and a second memory device in the data buffer;
b) performing a logic function on a first data word and an initial seed check value to produce an updated partial check value;
c) storing the first data word in a first location in the first memory device;
d) storing the updated partial check value in a first location in the second memory device;
e) performing the logic function on a second data word and the updated partial check value to produce a second updated partial check value;
f) storing the second data word in the first location in the second memory device;
and
g) storing the second updated partial check value in a second location in the first memory device.

5 more elements

In a computer system having a host computer, a storage subsystem and a plurality of storage devices, wherein the storage subsystem includes a control logic, a data buffer and a plurality of bus controllers, a method for calculating and storing a check value associated with a transfer of a block of data from one of the plurality of storage devices to the data buffer, the method comprising the steps of:

a) providing a first memory device and a second memory device in the data buffer;
b) performing a logic function on a first data word and an initial seed check value to produce an updated partial check value;
c) storing the first data word in a first location in the first memory device;
d) storing the updated partial check value in a first location in the second memory device;
e) performing the logic function on a second data word and the updated partial check value to produce a second updated partial check value;
f) storing the second data word in the first location in the second memory device;
and
g) storing the second updated partial check value in a second location in the first memory device.

5 more elements

In a computer system having a host computer, a storage subsystem and a plurality of storage devices, wherein the storage subsystem includes a control logic, a data buffer and a plurality of bus controllers, and wherein data is transferred between the host computer and the plurality of storage devices through the storage subsystem, the data buffer comprising:

a data bus;
a first memory device having a data input terminal, an address input terminal and a data output terminal, the data input terminal of the first memory device coupled to the data bus;
a second memory device having a data input terminal, an address input terminal and a data output terminal, the data input terminal of the second memory device coupled to the data bus;
a first logic function having a first input terminal coupled to the data output terminal of the first memory device, a second input terminal coupled to the data bus and an output terminal coupled to the second memory device;
a second logic function having a first input terminal coupled to the data output terminal of the second memory device, a second input terminal coupled to the data bus and an output terminal coupled to the first memory device;
and
a control circuit for alternately selecting between the first memory device and the second memory device
wherein the control circuit selects the first memory device to cause the first memory device to receive a first new data word from the data bus and to output a first existing check value to the first logic function, the first existing check value and the first new data word being input to the first logic function to calculate a first updated partial check value which is stored in the second memory device, and
the control circuit selects the second memory device to cause the second memory device to receive a second new data word from the data bus and to output a second existing check value to the second logic function, the second existing check value and the second new data word being input to the second logic function to calculate a second updated partial check value which is stored in the first memory device.

6 more elements

A data buffer comprising:

a data bus;
a first memory device having a data input terminal, an address input terminal and a data output terminal, the data input terminal of the first memory device coupled to the data bus;
a second memory device having a data input terminal, an address input terminal and a data output terminal, the data input terminal of the second memory device coupled to the data bus;
a first logic function having a first input terminal coupled to the data output terminal of the first memory device, a second input terminal coupled to the data bus and an output terminal coupled to the second memory device;
a second logic function having a first input terminal coupled to the data output terminal of the second memory device, a second input terminal coupled to the data bus and an output terminal coupled to the first memory device;
and
a control circuit for alternately selecting between the first memory device and the second memory device,
wherein the control circuit selects the first memory device to cause the first memory device to receive a first new data word from the data bus and to output a first existing check value to the first logic function, the first existing check value and the first new data word being input to the first logic function to calculate a first updated partial check value which is stored in the second memory device, and
the control circuit selects the second memory device to cause the second memory device to receive a second new data word from the data bus and to output a second existing check value to the second logic function, the second existing check value and the second new data word being input to the second logic function to calculate a second updated partial check value which is stored in the first memory device.

6 more elements

In a computer system having a host computer, a storage subsystem and a plurality of storage devices, wherein the storage subsystem includes a control logic, a data buffer and a plurality of bus controllers, and wherein data is transferred between the host computer and the plurality of storage devices through the storage subsystem, the data buffer comprising:

a data bus;
a first memory device having a data input terminal coupled to the data bus, an address input terminal and a data output terminal;
a second memory device having a data input terminal coupled to the data bus, an address input terminal and a data output terminal;
a first logic function having a first input terminal coupled to the data output terminal of the first memory device, a second input terminal coupled to the data bus and an output terminal coupled to the second memory device;
a second logic function having a first input terminal coupled to the data output terminal of the second memory device, a second input terminal coupled to the data bus and an output terminal coupled to the first memory device;
a control circuit for alternately selecting between the first memory device and the second memory device;
a first address counter having an input terminal and an output terminal coupled to the address input terminal of the first memory device;
a second address counter having an input terminal and an output terminal coupled to the address input terminal of the second memory device;
an address bus coupled to the input terminals of the first and second address counters;
a first multiplexer having a first data input terminal, a second data input terminal coupled to the data output terminal of the second logic function, and a data output terminal coupled to the data input terminal of the first memory device;
a second multiplexer having a first data input terminal, a second data input terminal coupled to the data output terminal of the first logic function, and a data output terminal coupled to the data input terminal of the second memory device;
a data bus coupled to the first data input terminal of the first multiplexer and the first data input terminal of the second multiplexer;
a third multiplexer having a first data input terminal coupled to the data output terminal of the first memory device, a second data input terminal coupled to the data output terminal of the second memory device, and a data output terminal;
and
a tristate buffer having an input terminal coupled to the data output terminal of the third multiplexer and an output terminal coupled to the data bus.

12 more elements

A data buffer comprising:

a data bus;
a first memory device having a data input terminal coupled to the data bus, an address input terminal and a data output terminal;
a second memory device having a data input terminal coupled to the data bus, an address input terminal and a data output terminal;
a first logic function having a first input terminal coupled to the data output terminal of the first memory device, a second input terminal coupled to the data bus and an output terminal coupled to the second memory device;
a second logic function having a first input terminal coupled to the data output terminal of the second memory device, a second input terminal coupled to the data bus and an output terminal coupled to the first memory device;
a control circuit for alternately selecting between the first memory device and the second memory device;
a first address counter having an input terminal and an output terminal coupled to the address input terminal of the first memory device;
a second address counter having an input terminal and an output terminal coupled to the address input terminal of the second memory device;
an address bus coupled to the input terminals of the first and second address counters;
a first multiplexer having a first data input terminal, a second data input terminal coupled to the data output terminal of the second logic function, and a data output terminal coupled to the data input terminal of the first memory device;
a second multiplexer having a first data input terminal, a second data input terminal coupled to the data output terminal of the first logic function, and a data output terminal coupled to the data input terminal of the second memory device;
a data bus coupled to the first data input terminal of the first multiplexer and the first data input terminal of the second multiplexer;
a third multiplexer having a first data input terminal coupled to the data output terminal of the first memory device, a second data input terminal coupled to the data output terminal of the second memory device, and a data output terminal;
and
a tristate buffer having an input terminal coupled to the data output terminal of the third multiplexer and an output terminal coupled to the data bus.

12 more elements

Dependencies are inferred from the claim text.

Method and apparatus for storing and retrieving error check information

Life of this patent

Method and apparatus for storing and retrieving error check information

Life of this patent

Abstract

Claims28