Fault-tolerant computer architecture

A computer designed to perform at least one given function, to detect failures and to further perform said function subsequent to the detection of a failure, said computer comprising data inputs and data outputs, two redundant processing chains each performing said function, and a monitoring device comprising a processor monitoring operation of said two processing chains, each processing chains comprising an acquisition circuit connected to said data inputs of said computer, a transmission circuit providing output data to be applied to said data outputs of said computer and a processor performing said function from data provided by said acquisition circuit in order to provide data applied to said transmission circuit, and monitoring operation of said monitoring device and of one other of said processing chains, each of said processing chains and said monitoring device supplying status data relating to the operating status of each of said processing chains and said monitoring device, the computer further comprising a voting device connected to said two processing chains and to said monitoring device so as to receive said status data in order to determine whether one of said two processing chains or said monitoring device is out of order, and a selection device applying to said data outputs of said computer only the output data provided by one of the two processing chains determined to be operating properly by said voting device.