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US 5,630,023 AGranted
Signal processor
AssigneeRicoh Company, Ltd.
InventorSugitaka Oteki
Life of this patent
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Abstract
A signal processor comprises a first shift register delaying an output from a neuron-simulated element by m cycles, a second shift register delaying an output from a neuron-simulated element by n cycles, wherein n is different from m, a logical product circuit for computing two logical products of the outputs from the shift registers, and a circuit for computing an error signal according to a teacher signal and the two logical products.
Claims4
A signal processor comprising:
- a coupling updating unit for updating a coupling coefficient according to a positive error signal and a negative error signal each generated depending on a teacher signal and output from a neuron-simulated element in which a plurality of neuron elements are connected to each other in a form like a network by combining said coupling updating unit with said neuron-simulated element;
- a first delaying unit for delaying an output from said neuron-simulated element by m cycles;
- a second delaying unit for delaying an output from said neuron-simulated element by n cycles wherein n is not equal to m;
- a first logical product unit for computing a logical product of an output from said first delaying unit above and an output from said second delaying unit;
- and
- a second logical product unit for computing a logical product of negation of an output from said first delaying unit and negation of an output from said second delaying unit.
3 more elements
A signal processor comprising:
- a coupling updating unit for updating a coupling coefficient according to a positive error signal and a negative error signal each generated depending on a teacher signal and output from a neuron-simulated element in which a plurality of neuron elements are connected to each other in a form like a network by combining said coupling updating unit with said neuron-simulated element;
- a first delaying unit for delaying an output from said neuron-simulated element by m cycles;
- a second delaying unit for delaying an output from said neuron-simulated element by n cycles wherein n is not equal to m;
- a logical product unit for computing a logical product of an output from said first delaying unit and negation of an output from said second delaying unit.
1 more element
Dependencies are inferred from the claim text.