Phase locked loop circuit

A phase locked loop circuit comprising:

• divider means for dividing a frequency of an input signal to a frequency designated by an external control signal, said external control signal being independent of a video signal provided to said phase locked loop circuit and representing a dividing ratio of said divider means, said external control signal being applied to a control signal input terminal of said divider means, said divider means outputting a divided frequency signal;
• a voltage generator for generating a voltage based on said external control signal representing said dividing ratio;
• a phase comparator for comparing a phase of a horizontal synchronizing signal of said video signal with a phase of said divided frequency signal output by said divider means, and thereby outputting a compared output signal;
• low pass filter means for extracting a direct current component from said compared output signal output by said phase comparator;
• an adder for adding said voltage generated by said voltage generator to an output of said low pass filter means, an output of said adder being provided to said oscillation means;
• and
• oscillation means for outputting an oscillating signal having a frequency that equals a product of a frequency of said horizontal synchronizing signal and said dividing ratio, which is based on said direct current component output from said low pass filter, said oscillating signal being applied to said divider means.