Fault management scheme for a cache memory
AssigneeDigital Equipment Corporation
InventorsNitin D. Godiwala, Kurt M. Thaller, Jeffrey A. Metzger, Barry A. Maskas
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Abstract
The present invention is directed to a method of managing a cache upon detection of an address TAG parity error, The cache includes a plurality of entries for storage of data, with each entry having a corresponding address TAG entry. The method includes the steps of performing a TAG parity check for each access to the cache, and upon detection of a parity error in an address TAG, disabling allocation of TAG entries for storage of new address TAGs. A signal indicating the TAG parity error is transmitted to an error correction mechanism.
Claims10
A method of managing a cache upon detection of an address TAG parity error, the cache including a plurality of entries for storage of data, and each entry having a corresponding address TAG entry, the method comprising the steps of:
- performing a TAG parity check for each access to the cache;
- upon detection of a parity error in an address TAG;
- disabling allocation of TAG entries for storage of new address TAGs;
- indicating the TAG parity error to an error correction mechanism;
- and
- while said allocation is disabled, allowing access to and modification of data and status bits of said plurality of cache entries such that the cache operates as if no error had been detected with the exception of said disabling allocation of TAG entries for storage of new address TAGS.
A cache memory system including a plurality of entries for storage of data, with each entry having a corresponding address TAG entry, said system comprising:
- means for performing a TAG parity check for each access to the cache;
- means for detecting a parity error in an address TAG;
- means responsive to detection of the parity error for disabling allocation of TAG entries for storage of new address TAGs;
- means for indicating the TAG parity error to an error correction mechanism;
- and
- means for providing continued access to the cache entries prior to correction of the TAG parity error as if no error had been detected with the exception of said disabling allocation of TAG entries for storage of new address TAGs.
Dependencies are inferred from the claim text.