Test mode setting circuit of test circuit for semiconductor memory

A test mode setting circuit comprising:

• a clock generator which generates predetermined internal control signals in response to an inverted RAS signal, inverted CAS signal, inverted WE signal and inverted OE signal which are synchronized with clock signals;
• a plurality of row address buffers which receive address signals other than an uppermost address signal among multiplexed address signals externally supplied, and distribute the received address signals as internal row address signals;
• a high voltage detection circuit which receives a high voltage higher than a power source voltage or a voltage of said uppermost address signal through a common input terminal, and which outputs a test mode setting signal when a voltage difference between the voltage received and said power source voltage becomes higher than a predetermined voltage;
• an uppermost row address buffer which receives through said common input terminal said high voltage or said uppermost address signal among said multiplexed address signals, and provides said uppermost address signal as an uppermost internal row address signal;
• and
• a voltage supplying means which operates such that, when, on receiving said high voltage through said common input terminal for setting a test mode, an upper stage transistor of two N-channel MOS transistors stacked one on the other in the uppermost row address buffer for said uppermost address signal becomes conductive through said high voltage, an uppermost internal control signal for said uppermost row address buffer among said internal control signals is supplied to a lower stage transistor connected to a ground thus causing said lower stage transistor to become a non-conductive state whereby a voltage across a gate electrode and a source electrode and a voltage across the gate electrode and a drain electrode of said upper stage transistor are rendered to be a level lower than said high voltage.