Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell array composed of a plurality of memory cells in and from which data are written and read for data groups, each of the data groups having a predetermined number of bits;
• and
• a control circuit responsive to data group control signals corresponding to each of the data groups and a write request signal, for generating an internal synchronized pulse signal on the basis of a logical result of one of the data control signals and the write request signal, the internal synchronized pulse signal being synchronized with a write start time and a write end time and further enabling write operation of the data group corresponding to one of the data group control signals, write operation being controlled on the basis of the internal synchronized pulse signal,
• wherein the internal synchronized pulse signal output by said control circuit includes a write start signal and a write end signal, and
• said control circuit outputs the write start signal when one of the data group control signals is at a select level and further the write request signal is at the write level, and thereafter outputs the write end signal when one of the data group control signals changes to a non-select level and further the write request signal changes to another level;
• however, even if the write request signal level changes, when a level of one of the data group control signals does not change, the write end signal is not outputted.

A semiconductor memory device comprising:

• a memory cell array composed of a plurality of memory cells in and from which data are written and read for data groups, each of the data groups having a predetermined number of bits;
• and
• a control circuit responsive to data group control signals corresponding to each of the data group and a write request signal, for generating an internal synchronized pulse signal on the basis of a logical result of one of the data control signals and the write request signal, the internal synchronized pulse signal being synchronized with a write start time and a write end time and further enabling write operation of the data group corresponding to one of the data group control signals, write operation being controlled on the basis of the internal synchronized pulse signal,
• wherein the internal synchronized pulse signal output by said control circuit includes a write start signal and a write end signal,
• said control circuit also controls read operation,
• said control circuit uses the write request signal in common for both writing and reading data, write operation being executed when the write request signal is at a write level and read operation being executed when the write request signal is at a read level, and
• said control circuit outputs the write start signal when one of the data group control signals is at a select level and further the write request signal is at the write level, and thereafter outputs the write end signal when one of the data group control signals changes to a non-select level and further the write request signal changes to another level;
• however, even if the write request signal level changes, when a level of one of the data group control signals does not change, the write end signal is not outputted.

A semiconductor memory device, comprising:

• a plurality of input/output terminal groups through each of which a data group composed of a predetermined number of bits is inputted and outputted;
• a memory cell array having a plurality of memory cell groups to each of which a plurality of the data groups can be written and read individually;
• a plurality of buses for connecting each of said memory cell groups and each of said input/output terminal groups;
• a plurality of data group control signal input terminals provided in correspondence to each of said input/output terminal groups, for receiving data group control signals each having a select level for inputting and outputting data group through its own corresponding input/output terminal group and a non-select level for inputting and outputting no data group;
• a write request signal input terminal for receiving a write request signal having a write enable level and a write disable level;
• and
• a control circuit responsive to a plurality of the data group control signals and the write request signal, for outputting a write start signal on the basis of a logical result of the select-level data group control signals and the enable-level write request signal, for writing the data group in the memory cell group through the input/output terminal group corresponding to the select-level data group control signal, and after that further controlling a write end signal in such a way that:
• when levels of the data group control signal related to the write operation and the write request signal both change to another level respectively, the write end signal is outputted to end the write operation;
• however, even if the write request signal level changes, when the data group control signal level does not change, the write end signal is not outputted.

A semiconductor memory device comprising:

• a memory cell array composed of a plurality of memory cells to and from which data are written and read by data groups, data being written during a write operation and data being read during a read operation;
• and
• a control circuit for obtaining a result of a logical operation on the basis of a write request signal and control signals for at least one of the data groups, to generate an internal synchronized pulse signal to control the write operation,
• wherein each of the data groups are composed of a plurality of bytes, and
• the internal synchronized pulse signal is synchronized with a write start time and a write end time.