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US 5,629,901 AGranted
Multi write port register
AssigneeInternational Business Machines Corporation
InventorStanley T. Ho
Life of this patent
Estimating the term…
Abstract
A multi-write port register is provided with a local clock buffer (LCB) to control a gate on the input port to reduce potential timing hazards. The LCB provides flexible logic function and is controlled by a clock and word-line inputs. In addition, the LCB may also have bit-line and/or field mask inputs. The LCB handles all the timing critical functions that all the Word Lines (WLs) previously performed in conventional multi-write port registers, thus providing a substantial performance increase.
Claims9
A multi-write port register file comprising:
- a plurality of gates connected between multiple write ports and a corresponding plurality of cells of the multi-write port register file;
- and
- a plurality of local clock buffers connected to control selected ones of said gates, the number of said local clock buffers corresponding to a number of write fields for the multi-write port register, each local clock buffer generating a write-enable signal to corresponding selected ones of said gates which write-enable signal is common among all cells contained in the same write field, said local clock buffer incorporating a fixed time delay between a system clock and an output of the local clock buffer to reduce timing hazards in writing data to the register in succeeding data cycles.
Dependencies are inferred from the claim text.