US 5,629,900 A · Semiconductor memory device operable to write data accurately at high speed

Abstract

A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

Claims7

Dependent claims

A semiconductor memory device, comprising:

a plurality of memory blocks each including a plurality of memory cells arranged in rows and columns;
first generator means responsive to a write instructing signal for generating a write control signal determining a data write operation timing;
second generator means responsive to an address signal for generating a block selection signal for selecting a memory block out of said plurality of memory blocks;
and
block control means provided corresponding and closely adjacent to respective memory blocks and each responsive to said block selection signal and said write control signal for generating a control signal for controlling a data write operation in a corresponding memory block.

2 more elements

A semiconductor memory device, comprising:

a first and a second memory cell arrays each including a plurality of memory blocks, each of said memory block including a plurality of memory cells arranged in rows and columns and having a high order data bit storage region and a low order data bit storage region;
first control signal generating means arranged between said first and second memory arrays at one side in outer periphery of the memory arrays, and responsive to an external control signal for generating a first write control signal for controlling data writing operation of said high order data bit storage region;
second control signal generating means provided between said first and second memory arrays in the outer periphery at another side opposing to said first control signal generating means, and responsive to said external control signal for generating a second write control signal for controlling a data writing operation of said low order data bit storage region;
block selection signal generating means responsive to an address signal for generating a block selection signal for selecting a memory block among said plurality of memory blocks;
first block write control means provided corresponding and proximate to each high order data bit storage region in respective memory blocks, and responsive to said first write control signal and said block selection signal for generating a block write control signal controlling operation of data writing in the high order data bit storage region in a corresponding memory block;
and
second block write control means provided corresponding and proximate to each low order data bit storage region of respective memory blocks, and responsive to said second write control signal and said block selection signal for generating a block write control signal for controlling an operation of data writing in the low order data bit storage region in a corresponding memory block.

4 more elements

A semiconductor memory device comprising:

a plurality of data input/output nodes;
a plurality of memory blocks each including a plurality of blocks, each of said blocks including a plurality of memory cells arranged in rows and columns and related to a different data input/output node from the other I/O blocks in each of said memory blocks;
a plurality of pairs of bit lines provided corresponding to the columns in each of said blocks and connecting memory cells on a corresponding column;
a plurality of column selection lines provided for each said pair of bit lines, for transferring a column selection signal to corresponding pairs of bit lines;
column decode means having output nodes less in number than said plurality of column selection lines, and response to an address signal for selecting a memory block and a column in each block in the selected memory block;
a plurality of connection means provided corresponding to output nodes of said column decode means, each for alternatively transferring a column selection signal onto one of successively adjacent column selection lines, a column selection line capable of receiving a column selection signal from one of successively adjacent connection means;
first write gate means provided for a pair of bit lines corresponding to a first column in a second block adjacent to a first block on each said memory block, and responsive to an output from a connection means provided for the last column in said first block and the first column in said second block, for connecting the pair of bit lines of the first column to a write data bus for the first block, said first column and said last column being adjacent with each other;
second write gate means responsive to an output of connection means provided for said first column and an adjacent second column in said second block for connecting the pair of bit lines of the first column to a write data bus for the second I/O block, in each of said memory block;
potential hold means provided in each said memory block, for holding the pair of bit lines of the first column to a predetermined potential only when both a first selection signal enabling said first write gate means and a second selection signal enabling said second write gate means are in an inactive state;
and
connection path defining means for determining connection path between said output nodes and said column selection lines such that the output nodes are connected to successively adjacent column selection lines except a defective column when the defective column connecting a defective memory cell is found to be present.

8 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device operable to write data accurately at high speed

Life of this patent

Semiconductor memory device operable to write data accurately at high speed

Life of this patent

Abstract

Claims7