US 5,629,898 AGranted

Dynamic memory device, a memory module, and a method of refreshing a dynamic memory device

AssigneeHitachi, Ltd.

InventorsYouji Idei, Katsuhiro Shimohigashi, Masakazu Aoki, Hiromasa Noda, Katsuyuki Sato, Hidetoshi Iwai, Makoto Saeki, Jun Murata, Yoshitaka Tadaki, Toshihiro Sekiguchi, Osamu Tsuchiya

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Abstract

A period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry signal outputted from the refresh address counter is divided by a divider. For each of said plurality of word lines assigned with the refresh address, one of a short period corresponding to an output pulse of a timer or a long period corresponding to the divided pulse from the divider is stored in a storage circuit as refresh time setting information. A memory cell refresh operation to be performed by the refresh address is made valid or invalid for each word line according to the refresh time setting information stored in the storage circuit and the refresh time setting information itself is made invalid by the output pulse of the divider.

Claims15

Dependent claims

A dynamic memory device formed on a semiconductor substrate, said dynamic memory device having a plurality of memory blocks, a refresh address counter for receiving a periodic pulse signal to output a refresh address signal, a controller for receiving said refresh address signal, and a word line select circuit for receiving said refresh address signal;

said plurality of memory blocks including a first memory block having a plurality of first word lines and a plurality of first dynamic memory cells each of which is coupled to corresponding one of said plurality of first word lines and arranged in a matrix and a second memory block having a plurality of second word lines and a plurality of second dynamic memory cells each of which is coupled to corresponding one of said plurality of second word lines and arranged in a matrix;
said controller including a refresh period retention circuit for holding information about refresh periods each of which correspond to said plurality of first word lines and said plurality of second word lines;
and
wherein, if said refresh period retention circuit has information that a refresh period of one of said plurality of first word lines corresponding to said refresh address signal is a first refresh period and a refresh period of one of said plurality of second word lines corresponding to said refresh address signal is a second refresh period longer than said first refresh period, said controller performs one of control operations, said control operations including a first operation such that said word line select circuit simultaneously selects said one of said plurality of first word lines corresponding to said refresh address signal and said one of said plurality of second word lines corresponding to said refresh address signal and a second operation such that said word line select circuit selects said one of said plurality of first word lines corresponding to said refresh address signal and does not select said one of said plurality of second word lines corresponding to said refresh address signal.

1 more element

A dynamic memory device formed on one semiconductor substrate, said dynamic memory device having a memory array arranged with dynamic memory cells in a matrix,

an address select circuit for selecting said memory cells, and
a controller for receiving one of a control signal supplied from an external terminal and a timing signal to determine an operating mode and form a corresponding timing signal;
said dynamic memory device comprising an adaptive refresh controller having
a timer circuit for generating a periodic pulse corresponding to a refresh period shorter than a shortest information retention time of those of said dynamic memory cells,
a refresh address counter for counting an output pulse of said timer circuit to generate a refresh address to be assigned commonly to a plurality of word lines,
a divider for dividing a carry signal generated by said refresh address counter, and
a storage circuit adapted to store one of refresh time setting information corresponding to the output pulse of said timer circuit and refresh time setting information corresponding to an output pulse of said divider for each of said plurality of word lines assigned to said refresh address,
wherein a refresh operation to be performed by said refresh address is made valid or invalid for each of said plurality of word lines according to said refresh time setting information stored in said storage circuit and said refresh time setting information is made invalid by said output pulse of said divider.

5 more elements

A memory module comprising:

a plurality of dynamic memory devices formed on a semiconductor substrate, said plurality of dynamic memory devices having a memory array arranged with dynamic memory cells in a matrix, an address select circuit for selecting said dynamic memory cells, and a controller for receiving one of a control signal supplied from an external terminal and a timing signal to determine an operating mode and form a corresponding timing signal;
and
an adaptive refresh controller having
a timer circuit for generating a periodic pulse corresponding to a refresh period shorter than a shortest information retention time of those of said dynamic memory cells formed on said plurality of dynamic memory devices,
a refresh address counter for counting an output pulse of said timer circuit to generate a refresh address of said plurality of dynamic memory devices,
a divider for dividing a carry signal generated by said refresh address counter, and
a storage circuit for storing refresh time setting information corresponding to one the output pulse of said timer circuit and the divided output of said divider according to the shortest information retention time of those of the dynamic memory cells connected to a word line to be selected by said refresh address in said plurality of dynamic memory devices, said storage circuit being read by said refresh address;
wherein a refresh operation to be performed by said refresh address is made valid or invalid for each of said plurality of dynamic memory devices according to said refresh time setting information stored in said storage circuit and said refresh time setting information is made invalid by said output pulse of said divider.

5 more elements

Dependencies are inferred from the claim text.