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US 5,629,897 AGranted
Synchronous semiconductor memory device having a mode requiring an internal clock signal and a mode not requiring the internal clock signal
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHisashi Iwamoto, Yasuhiro Konishi
Life of this patent
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Abstract
A refresh control circuit of a DLL circuit responds to an auto refresh detection signal AR and a self refresh detection signal SR to inhibit input of clock signals ECLK and RCLK to a phase comparator and to a voltage control delay circuit. The DLL circuit can be stopped in a mode where an internal clock signal is not required to reduce power consumption.
Claims5
A synchronous semiconductor memory device having a mode requiring an internal clock signal and a mode not requiring said clock signal, comprising:
- a plurality of memory arrays including a plurality of memory cells arranged in a matrix,
- a delay circuit controllable of a delay time for delaying an external clock signal and providing the delayed signal as said internal clock signal,
- a phase control circuit to detect a phase difference of said external clock signal and said internal clock signal for controlling a delay time of said delay circuit so that said phase difference is eliminated,
- a data input/output circuit for carrying out data input and output between a selected memory cell in said plurality of memory arrays and an external source in synchronization with said internal clock signal, and
- a signal control circuit for inhibiting input of said external clock signal to said delay circuit and said phase control circuit for a predetermined time period in response to designation of said mode not requiring said clock signal.
2 more elements
Dependencies are inferred from the claim text.