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US 5,629,896 AGranted
Write controlled address buffer
AssigneeSGS-Thomson Microelectronics S.A.
InventorDavid C. McClure
Life of this patent
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AssigneeSGS-Thomson Microelectronics S.A.
InventorDavid C. McClure
Estimating the term…
An input buffer, for an asynchronous integrated memory circuit incorporating a memory circuit, including a latch circuit controlled by a write enable signal is disclosed. The input stage of the input buffer is connected to a pass gate, which is controlled by the write enable signal so that the pass gate is nonconductive when the write enable signal is active. The output of the pass gate is connected to an input of the latch circuit. The latch circuit is controlled by the write enable signal so that the signal present on the input of the latch is latched when the write enable signal is active. From an output of the latch circuit are obtained true and complementary signals, which are applied to outputs of the buffer circuit. As a result, when the write enable signal is active, the signal present on the input of the buffer is latched and presented to the outputs of the buffer, and the latch circuit is isolated from the input of the buffer until the write cycle is terminated.
An input buffer circuit in an asynchronous integrated memory circuit having a first input terminal receiving an input signal and a first output terminal for communicating a signal depending from the logic level of the input signal, comprising:
A method for controlling the buffering of an input signal at an input terminal of an asynchronous integrated memory circuit, said integrated circuit incorporating a memory circuit having a write enable input for receiving a write enable signal, comprising:
An asynchronous integrated memory device comprising:
Dependencies are inferred from the claim text.