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US 5,629,886 AGranted
Method and structure for providing fast propagation of a carry signal in a field programmable gate array
AssigneeXilinx, Inc.
InventorBernard J. New
Life of this patent
Estimating the term…
Abstract
A carry logic circuit for a field programmable gate array (FPGA) which allows a carry input signal to be propagated through the carry logic circuit without passing through a multiplexer of another series connected circuit element. The carry logic circuit uses a function generator of the FPGA to provide a propagate signal in response to first and second input signals provided to the carry logic circuit. Also described are methods for performing a carry logic function in an FPGA.
Claims11
A field programmable gate array having at least one carry logic circuit comprising:
- a first carry chain which propagates a first plurality of carry chain signals;
- a second carry chain which propagates a second plurality of carry chain signals;
- a first line coupled to receive a carry input signal;
- a plurality of multiplexers, each having a first input terminal coupled to the first carry chain, a second input terminal coupled to the second carry chain, a control terminal coupled to the first line, and an output terminal which receives one of the first plurality of carry signals or one of the second plurality of carry signals in response to the carry input signal on the first line;
- and
- a plurality of programmable function generators coupled to the first and second carry chains, wherein the function generators control the propagation of the first and second plurality of carry chain signals is through the first and second carry chains.
3 more elements
A method of performing a carry logic function in a field programmable gate array (FPGA), comprising the steps of:
- providing first and second input signals to a function generator to create a propagate signal;
- providing the propagate signal to control a first multiplexer and a second multiplexer;
- providing a first carry chain signal to the first multiplexer;
- providing a second carry chain signal to the second multiplexer;
- if the first input signal has the same value as the second input signal, then routing the first input signal through the first multiplexer as a third carry chain signal and routing the first input signal through the second multiplexer as a fourth carry chain signal;
- if the first input signal does not have the same value as the second input signal, then routing the first carry chain signal through the first multiplexer as the third carry chain signal and routing the second carry chain signal through the second multiplexer as the fourth carry chain signal;
- providing a carry input signal to control a third multiplexer;
- routing the third carry chain signal through the third multiplexer as a local carry input signal if the carry input signal has a first value;
- and
- routing the fourth carry chain signal through the third multiplexer as the local carry input signal if the carry input signal has a second value.
7 more elements
A field programmable gate array (FPGA) having at least one least one carry logic circuit comprising:
- means for providing a first input signal (Ai);
- means for providing a second input signal (Bi);
- a first carry chain lead coupled to receive a first carry chain signal (CAi);
- a second carry chain lead coupled to receive a second carry chain signal (CBi);
- a third carry chain lead;
- a fourth carry chain lead;
- a carry input lead coupled to receive a carry input signal (Cin);
- a local carry input lead for providing a local carry input signal (Ci+1) to a logic forming element of another carry logic circuit;
- a first multiplexer (103) for connecting one of said first input lead and said first carry chain lead to said third carry chain lead;
- a second multiplexer (104) for connecting one of said first input lead and said second carry chain lead to said fourth carry chain lead;
- a function generator coupled to the first and second input leads, wherein the function generator generates a propagate signal which is provided to said first and second multiplexers, thereby causing said first and second multiplexers to connect said first input lead to said third and fourth carry chain leads when and only when said first input value is equal to said second input value, and to connect said first carry chain lead to said third carry chain lead and to connect said second carry chain lead to said fourth carry chain lead when and only when said first input signal is not equal to said second input signal;
- and
- a third multiplexer (132) for coupling one of said third carry chain lead and said fourth carry chain lead to the local carry input terminal (Ci+1) in response to said carry input signal (Cin).
10 more elements
Dependencies are inferred from the claim text.