Nested maximum space computation and efficient generation of nested shape complementation
AssigneeInternational Business Machines Corporation
InventorYoung O. Kim
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AssigneeInternational Business Machines Corporation
InventorYoung O. Kim
Estimating the term…
A method of nested maximum space computation is used for the processing of shapes in design data for integrated circuits and printed circuit electronic packages. This method determines the complement of a design level without unnecessary flattening or denesting thereby reducing the processing time and the volume of the output data. Native shapes are first expanded by one-half the maximum space ground rule value to get the expanded native shapes. The nested shape complementation method is applied to the expanded native shapes to get the error candidate shapes. The error candidate shapes indicate areas that are possible violations. Next, the expanded native shapes are subtracted from the error candidate shapes to get the real error shapes. The nested shape complementation method finds the regions between shapes in a hierarchical design without denesting. For each cell that does not have transforms of other cells, the nested shape complementation method finds the cell's proper frame and uses that frame and the cell's native shapes to create complemented shapes. For each cell with transforms of other cells, the nested shape complementation method finds the cell's proper frame and uses that frame, the cell's native shapes, and its transformed cell's frames to create complemented shapes. The complemented shapes are added to the cell as native shapes on a new design level.
A computer-implemented method of efficiently generating nested complemented shapes of a physical design for integrated circuit chip or electronic package designs without flattening or denesting hierarchal design data of the physical design comprising the steps of:
A computer-implemented method of efficiently determining violations of a maximum space restriction for a physical design of integrated circuit chip or electronic package designs without flattening or denesting hierarchial design data of the physical design comprising the steps of:
A computer-implemented method of efficiently generating nested complemented shapes of a hierarchical design data file without flattening or denesting hierarchal design data comprising the steps of:
Dependencies are inferred from the claim text.