Method for determining timing delays associated with placement and routing of an integrated circuit

A method for determining a wireload model associated with placement of an integrated circuit, the method comprising the steps of:

• inputting a plurality of circuit elements and interconnection therebetween into a computer;
• defining at least one group of circuit elements and assigning a region on an integrated circuit for each one of said at least one group;
• placing subgroups of said circuit elements of each of said at least one group into a location within its respective region;
• estimating an area of each of said region;
• determining an average wire length per fanout for each said at least one group from empirical data during a floorplanning step and prior to performing an actual place and route step;
• using said determined average wire length to determine the wireload model as a function of said estimated area;
• and
• using said wire load model to design said integrated circuit.

A method for determining parasitics associated with routing of an integrated circuit, the method comprising the steps of:

• inputting a plurality of circuit elements and interconnection therebetween into a computer;
• defining at least one group of circuit elements and assigning a region on an integrated circuit for each one of said at least one group;
• placing subgroups of said circuit elements of each of said at least one group into a location within its respective region;
• estimating an area of each of said region;
• determining RC time constant effects corresponding to routing of said integrated circuit, said RC time constant effects being distinguished between those that are intra regional and those that are inter regional;
• providing a parasitic to include said RC time constant effects;
• and
• using said parasitic to include said RC time constant effects while in a floor planning stage and prior to performing a place and route step;
• and
• using said parasitic to design said integrated circuit.