A code conversion circuit, comprising:
- a first decoder including means for receiving an a-bit binary input representing a value i, where i is an integer.gtoreq.0;
- said first decoder including b first output lines being ordinally numbered, where b.ltoreq.2.sup.a ;
- said first decoder further including means responsive to said a-bit binary input for producing a plurality of first output signals on said b first output lines;
- said plurality of first output signals including a signal "1" only on an (i+1)th one of said b first output lines and a signal "0" on a remainder of said b first output lines;
- a second decoder including means for receiving said first output signals;
- said second decoder including a plurality of second output lines being ordinally numbered;
- said second decoder further including means responsive to said plurality of first output signals for producing a plurality of second output signals;
- said plurality of second output signals including a signal "1" on a second output line i-th from a first end of said plurality of second output lines and on each of said plurality of second output lines from said second output line i-th from said first end to a one of said second output lines located at said first end, and a signal "0" on a remainder of said second output lines;
- said second decoder being segmented into a plurality of blocks, each of said plurality of blocks including a different set of ordinally numbered ones of said second output lines;
- said plurality of blocks being ordered from a lowest ordered block to a highest ordered block;
- said lowest ordered block including said first end of said plurality of second output lines;
- each of said plurality of blocks including state determining means for selectively placing an associated one of said plurality of blocks in one of a first state, a second state and a third state;
- said first state wherein a signal "1" is developed on all of said plurality of second output lines included in said associated one of said plurality of blocks;
- said second state wherein a signal "1" is developed on a second output line i-th from said first end of said plurality of second output lines and all of said second output lines nearer to said first end which are included in said associated one of said plurality of blocks, and a signal "0" is developed on a remainder of said plurality of second output lines included in said associated one of said plurality of blocks;
- said third state wherein a signal "0" is developed on all of said plurality of second output lines included in said associated one of said plurality of blocks;
- block control signal generating means responsive to said a-bit binary input for producing and supplying block control signals including means for controlling respective ones of said state determining means in each of said plurality of blocks;
- said block control signals each being one of a first, a second and a third block control signal to place a respective block in one of said first state, said second state and said third state respectively;
- said block control signal generating means including means for supplying said second block control signal to said state determining means in an n-th block of said plurality of blocks to which said second output line i-th from said first end belongs;
- said block control signal generating means including means for supplying said first block control signal to said state determining means in each of a first to a (n-1)th block of said plurality of blocks;
- and
- said block control signal generating means including means for supplying said third block control signal to said state determining means in each of a (n+1)th and higher order blocks of said plurality of blocks.