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US 5,629,696 AGranted
Parallel to serial data converter
AssigneeCanon Kabushiki Kaisha
InventorsSomei Kawasaki, Masami Iseki, Hironari Ebata
Life of this patent
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Abstract
In a parallel to serial converter, data is inputted in parallel to a set of latches in a cycle of an inputted first clock signal. A second clock signal having a 50% duty cycle is generated according to the inputted first clock signal. The second clock signal is delayed to output a third clock signal and a switching unit selects and outputs the latched data in response to the second and third clock signals.
Claims9
A parallel/serial converter comprising:
- means for inputting a first clock signal;
- a plurality of latch means for latching parallel data with a cycle of the first clock signal;
- means for generating a second clock signal having a duty ratio of 50% in accordance with the input first clock signal;
- delay means for delaying the second clock signal to output a third clock signal;
- and
- switching means for selecting and outputting data latched by said plurality of latch means in accordance with said second and third clock signals.
3 more elements
An image forming apparatus comprising a parallel/serial converter, said parallel/serial converter including:
- means for inputting a first clock signal;
- a plurality of latch means for latching parallel data with a cycle of the first clock signal;
- means for generating a second clock signal having a duty ratio of 50% in accordance with the input first clock signal;
- delay means for delaying the second clock signal to output a third clock signal;
- and
- switching means for selecting and outputting data latched by said plurality of latch means in accordance with said second and third clock signals.
3 more elements
Dependencies are inferred from the claim text.