Apparatus and method for power reduction in dRAM units
AssigneeTexas Instruments Incorporated
InventorsVinod J. Menezes, Subramani Kengeri, Raghava Madhu
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AssigneeTexas Instruments Incorporated
InventorsVinod J. Menezes, Subramani Kengeri, Raghava Madhu
Estimating the term…
In a DRAM unit in which the substrate bias voltage is maintained within predetermined limits by a of voltage detectors and a charge pump, a third voltage detector is provided which detects a intermediate substrate bias voltage level that is within the voltage range identified by the pair of voltage detectors. When the third voltage level detects that the intermediate substrate bias voltage has been traversed, the charge pump is activated at a reduced level to drive the substrate bias voltage to recross the intermediate substrate bias voltage level. This technique permits the DRAM unit to operate in a stand-by mode at a lower power level, especially in a standby mode of operation, than when the substrate bias voltage is maintained only by the two voltage limit detectors and a single power level charge pump.
Apparatus for controlling the substrate bias voltage in a DRAM unit, said apparatus comprising:
Dependencies are inferred from the claim text.