Adjustable timer circuit

An adjustable timer circuit comprising:

• a timing capacitor;
• a source of timing capacitor current having a magnitude which is derived from a reference voltage, with the timing capacitor current causing a voltage on the capacitor to change from a first state to a second state;
• a voltage comparator connected to compare a voltage on the timing capacitor with a comparison voltage and producing an output when the voltage on the capacitor is at the second state;
• a reset circuit for causing the voltage on the timing capacitor to return to the first state in response to the comparator output;
• and
• a frequency divider responsive to the comparator output for providing a plurality of frequency divided outputs;
• a decoder circuit for decoding selected ones of the frequency divided outputs based upon selected decode parameters;
• and
• a plurality of programmable non-volatile memory cells for storing the selected decode parameters.

A timer circuit comprising:

• a timing capacitor;
• a current source configured to produce a reference current having a magnitude derived from a first reference voltage, with the current source comprising first adjust circuitry configured to adjust the magnitude of the reference current in response to a mode control signal;
• a current divider operably coupled to the current source and to the timing capacitor, said current divider being configured to produce a unidirectional timing capacitor current in the timing capacitor having a magnitude which is equal to the magnitude of the reference current divided by a value greater than one, with the value being adjustable in response to the mode control signal;
• a comparator circuit connected to compare a magnitude of a voltage produced across the timing capacitor with a comparison voltage and producing a comparator output based upon the comparison;
• and
• output circuitry configured to produce a timer output in response to the comparator output.

A timer circuit comprising:

• a timing capacitor;
• a current source configured to produce a reference current having a magnitude derived from a first reference voltage;
• a current divider operably coupled to the current source and to the timing capacitor, said current divider being configured to produce a timing capacitor current for the timing capacitor having a magnitude which is equal to a magnitude of the reference current divided by a value greater than one, with the current divider comprising a first current mirror having a current mirror input and a current mirror output, with the current mirror input comprising a first transistor structure and with the current mirror output comprising a second transistor structure, with the first transistor structure having an effective ratio of channel width to channel length which is greater than an effective ratio of channel width to channel length of the second transistor structure, and with one of the first and second transistor structures comprising first and second sub-transistors, with a drain and a gate of the second sub-transistor coupled to a gate of the other of the first and second transistor structures, and with the first current mirror comprising first adjust circuitry for selectively coupling and decoupling the first and second sub-transistors in parallel in response to a mode control signal;
• a comparator circuit connected to compare a magnitude of a voltage produced across the timing capacitor with a comparison voltage and producing a comparator output based upon the comparison;
• and
• output circuitry configured to produce a timer output in response to the comparator output.

A timer circuit comprising:

• a timing capacitor;
• a current source configured to produce a reference current having a magnitude derived from a first reference voltage;
• a current divider operably coupled to the current source and the timing capacitor, the current divider being configured to produce a timing capacitor current in the timing capacitor having a magnitude which is equal to the magnitude of the reference current divided by a value greater than one;
• a comparator circuit for comparing a magnitude of a voltage produced across the timing capacitor with a comparison voltage and producing a comparator output based upon the comparison;
• output circuitry configured to produce a timer output in response to the comparator output, with the timer output having a start point and a stop point and wherein the timing capacitor current causes the voltage across the timing capacitor to change from a first level at the start point to a second level at the stop point;
• retrigger circuitry configured to cause the voltage across the timing capacitor to change from the second level to the first level at which time the timer output is at the timer output stop point;
• and
• a frequency divider circuit operably coupled to the output circuitry, said frequency divider circuit being configured to produce a plurality of frequency divided outputs, each having a period which is a different multiple of a period between the timer output start and stop points.

A timer circuit comprising:

• a timing capacitor;
• a current source configured to produce a reference current having a magnitude which is relatively independent of a primary supply voltage for the timer circuit;
• a current divider, operably coupled to the current source, the current divider being configured to produce a unidirectional capacitor current for the timing capacitor, with the capacitor current having a magnitude which is equal to the magnitude of the reference current divided by a value greater than one;
• a comparator circuit, operably coupled to the timing capacitor, the comparator circuit configured to provide a comparator output indicative of a magnitude of a voltage across the timing capacitor relative to a threshold voltage;
• output circuitry, operably coupled to the comparator circuit, said output circuitry configured to produce a timer output in response to the comparator output, with the timer output having a start point and a stop point and wherein the capacitor current causes the voltage across the timing capacitor to change from a first level at the start point to a second level;
• retrigger circuitry configured to cause the voltage across the timing capacitor to change from the second level to the first level at which time the timer output is at the stop point;
• and
• frequency divider circuitry configured to produce a plurality of frequency divided outputs, each having a period which is a different multiple of a period between the timer output start and stop points.

A method of generating a timing signal comprising the following steps:

• generating a reference current;
• receiving a mode control signal;
• dividing the reference current by a divisor value to produce a unidirectional output current, with the divisor value being switchable between at least two values based upon a state of the mode control signal;
• applying the output current to a timing capacitor so as to cause a voltage across the capacitor to change from a first level to a second level;
• causing the voltage across the capacitor to change from the second level to the first level;
• and
• generating a timing signal having a period which is set by a time required for the voltage capacitor to change from the first level to the second level.

A method of generating a timing signal comprising the following steps:

• receiving a reference voltage which is relatively constant in magnitude;
• generating a reference current having a magnitude which is related to the reference voltage magnitude;
• dividing the reference current by a positive divisor value greater than one to produce an output current;
• applying the output current to a timing capacitor so as to cause a voltage across the capacitor to change from a first level to a second level;
• providing a comparison voltage having a magnitude which is related to the magnitude of the reference voltage;
• comparing the voltage across the capacitor with the comparison voltage to determine when the voltage across the capacitor is at the second level;
• causing the voltage across the capacitor to change from the second level to the first level;
• and
• generating a timing signal having a period which is set by a time required for the voltage capacitor to change from the first level to the second level.

A method of generating a timing signal comprising the following steps:

• generating a reference current;
• dividing the reference current by a positive divisor value greater than one to produce an output current;
• applying the output current to a timing capacitor so as to cause a voltage across the capacitor to change from a first level to a second level;
• providing a comparison voltage having a magnitude which is related to the magnitude of a reference voltage;
• comparing the voltage across the capacitor with the comparison voltage to determine when the voltage across the capacitor is at the second level;
• causing the voltage across the capacitor to change from the second level to the first level;
• generating a timing signal having a period which is controlled by a time required for the voltage capacitor to change from the first level to the second level;
• frequency dividing the timing signal so as to produce a plurality of frequency divided outputs;
• and
• decoding selected ones of the frequency divided outputs based upon selected decode parameters.